Patent
1994-11-03
1997-05-06
Sheikh, Ayaz R.
395737, 395868, G06F 1326
Patent
active
056280181
ABSTRACT:
The object of the present invention is to provide an interruption processing apparatus which allows for improvements in operational speed and offers flexibility for a variety of systems, while using a lower amount of hardware. When an interruption occurs, then for the present invention shown in FIG. 2 , the corresponding interruption request flag in the interruption control register 1 in the group interruption control unit 5 is set. The interruption request unit 2 then outputs the interruption signal to the CPU 6 based on the interruption request flag. The interruption level arbitration unit 3 adjusts any conflict with other group control units and outputs, as the arbitration result, a signal showing whether output is possible or not for the interruption signal. The group number output unit 4 then outputs the fixed group number for the group in accordance with the arbitration result in response to access from the CPU 6. Once the CPU 6 receives the interruption request signal, no matter from what group interruption control unit the interruption was from, it activates the start of a program starting at the same address.
REFERENCES:
patent: 4332011 (1982-05-01), Epstein et al.
patent: 4484263 (1984-11-01), Olson et al.
patent: 4615019 (1986-09-01), Bonci
patent: 4628449 (1986-12-01), Zardiackas
patent: 4644465 (1987-02-01), Imamura
patent: 4748586 (1988-05-01), Bonci
patent: 4779195 (1988-10-01), James
patent: 4796176 (1989-01-01), D'Amico et al.
patent: 5119496 (1992-06-01), Nishikawa et al.
patent: 5146595 (1992-09-01), Fujiyama et al.
patent: 5179704 (1993-01-01), Jibbe et al.
patent: 5212796 (1993-05-01), Allison
patent: 5261109 (1993-11-01), Cadambi et al.
patent: 5265215 (1993-11-01), Fukuda et al.
patent: 5283904 (1994-02-01), Carson et al.
patent: 5321818 (1994-06-01), Wendling et al.
patent: 5325536 (1994-06-01), Chang et al.
patent: 5481728 (1996-01-01), Matsutani
Hitachi Single Chip MicroComputer, 1989, H8/532 HD6475328, HD6435328 Hardware Manual, pp. 73-75 (with translation).
Intel Corporation, Intel 8096KB Programmer's Reference Manual, 1988, p. 7-11, p. 8-1, to p. 8-11.
Motorola Inc., MC68040 32-Bit Third-Generation Microprocessor, 1989, pp. 2-4 to 2-5, pp. 3-17 to 3-18.
NEC Corporation V Series Microprocessor Data Book, 1989, pp. 104-106 (with translation).
"Interrupt Service Allocation Technique for the Micro Channel Bus", IBM Technical Disclosure Bulletin, vol. 33, No. 1A, Jun. 1990.
Higaki Nobuo
Matsuzaki Toshimichi
Matsushita Electric - Industrial Co., Ltd.
Sheikh Ayaz R.
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