Data processing apparatus for virtual memory system

Details Data processing apparatus for virtual memory system Data processing apparatus for virtual memory system

1983-01-28

1986-12-09

Heckler, Thomas M.

Boots, shoes, and leggings

G06F 934

Patent

active

046284516

ABSTRACT:
A data processing apparatus for a virtual memory system including a logical address register, a real address register, a paged address translation table and an address translation buffer in which a map of a fraction of the paged address translation table is stored columnwise. Upon checking address translatability of a logical address into a real address, a bit of a translation control word contained in the column of the address translation buffer relevant to that logical address indicates whether or not a succeeding logical address is susceptible to the address translation. Necessity to pretest the address translatability of every logical address is obviated. System overhead is considerably reduced.

REFERENCES:
patent: 4145738 (1979-03-01), Inoue et al.
patent: 4170039 (1979-10-01), Beacom et al.
patent: 4218743 (1980-08-01), Hoffman et al.
patent: 4356549 (1982-10-01), Chueh
patent: 4373179 (1983-02-01), Katsumata
patent: 4466056 (1984-08-01), Tamahashi

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