Data processing apparatus for selectively posting write cycles u

Details Data processing apparatus for selectively posting write cycles u Data processing apparatus for selectively posting write cycles u

1991-05-07

1994-07-05

Kulik, Paul V.

Boots, shoes, and leggings

364221, 3642303, 364DIG1, G06F 1200

Patent

active

053275454

ABSTRACT:
A microcomputer system employing an 80386 CPU and an 82385 cache controller has the capability of functioning with dynamic bus sizing (where the CPU interacts with devices which may or may not be 32-bits wide), as well as posted write capability. Unfortunately, the two capabilities have the possibility of an incompatibility if a write cycle is posted to a device which cannot transfer 32 bits on a single cycle. The present invention provides logic to overcome this incompatibility. An address decoder is provided to decode the tag portion of an address asserted on a CPU local bus to determine if the asserted address is inside or outside a range of addresses which define cacheable devices. Any cacheable device is by definition 32 bits wide and therefore posted writes are allowed only to cacheable devices. Accordingly, the microcomputer system employing the invention posts write cycles to cacheable devices; write cycles to non-cacheable devices are inhibited from being posted.

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B. C. Cole, How A Cache Control Chip Supercharges 386 Processor, Electronics vol. 60, No. 12, Jun. 11, 1987, pp. 74-76.
D. Jones et al., The 68030; Electronics & Wireless World vol. 93, No. 1621, Nov. 1987, pp. 1121-1123.

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