Data processing apparatus for performing parallel decoding and p

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364260, 3642613, 3642629, 364938, 36493141, 3649483, 3649469, 364DIG1, 395550, 395800, G06F 930

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052029670

ABSTRACT:
A data processing apparatus for decoding and executing instructions in a parallel manner in a variable word length instruction format. A plurality of decoders is used in which while the primary instruction decoder is decoding an instruction, the probability of parallel decoding of the next instruction is detected, so that the primary instruction decoder and a secondary instruction decoder decode a variable word length instruction and a fixed word length instruction, respectively, in a parallel manner. A conditional branch instruction of a fixed word length and the subsequent instruction of a variable word length are decoded and executed in a parallel manner to increase the speed at which the conditional branch instruction is executed.

REFERENCES:
patent: 4295193 (1981-10-01), Pomerene
patent: 4476525 (1984-10-01), Ishii
patent: 4752873 (1988-06-01), Shonai et al.
patent: 4837678 (1989-06-01), Culler et al.
patent: 4847755 (1989-07-01), Morrison et al.
Miller et al., "Floating-Duplex Decode and Execution of Instruction", IBM Technical Disclosure Bulletin, vol. 23, No. 1, pp. 409-412, Jun. 1980.

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