Patent
1997-03-27
1999-05-25
Lall, Parshotam S.
395395, 395562, G06F 938
Patent
active
059076941
ABSTRACT:
The present data processing apparatus effects the pipeline operation for each of the machine cycle time with a plurality of pipeline stages processed in parallel. With respect to a load & extension instruction for instructing with the single instruction a first processing portion for reading the data shorter than the register length from RAM 19 and a second processing portion for zero-extending or the sign-extending the data into the register length, a zero-extension or a sign-extension operation in the second processing operation is executed, in a pipeline stream different from the pipeline stream where a first processing operation is executed or in a pipeline stage different from the pipeline stage where the reading from the storage portion of the first processing operation is executed.
REFERENCES:
patent: 5420992 (1995-05-01), Killian et al.
patent: 5450607 (1995-09-01), Kowalczyk et al.
patent: 5560039 (1996-09-01), Dulong
patent: 5590352 (1996-12-01), Zuraski, Jr. et al.
patent: 5638526 (1997-06-01), Nakada
An English Language Summary of JP 7-262005.
An English Language Abstract of JP 2-250117.
Higaki Nobuo
Miyaji Shinya
Nishimichi Yoshito
Suzuki Masato
Tominaga Nobuki
Lall Parshotam S.
Matsushita Electric - Industrial Co., Ltd.
Vu Viet
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