Data processing apparatus for address substitution

Details Data processing apparatus for address substitution Data processing apparatus for address substitution

1983-12-27

1986-07-29

Hoffman, James R.

Boots, shoes, and leggings

G06F 1210, G06F 1212

Patent

active

046033998

ABSTRACT:
Data from a patch memory (23) is substituted for that in a system ROM (9) by applying high order addresses to a standard PLA (19) having word lines (FIG. 3, 50a-50p). The address orders are separately applied to EXCLUSIVE OR circuits (27a-27g). The PLA (19) is personalized to activate line (21) at addresses to be substituted and to provide logical zeros to the EXCLUSIVE OR circuits (27a-27g) which change during the patch. Only one word line is required for each continuous patch, which vary in size on a patch-by-patch basis. The circuit is fast and efficient. It can be used for a wide variety of memory substitution applications.

REFERENCES:
patent: 4028678 (1977-06-01), Moran
patent: 4141068 (1979-02-01), Mager et al.
patent: 4319343 (1982-03-01), Powell
patent: 4400798 (1983-08-01), Francis et al.
"Replacing Portions of Read-Only Store Modules with Random-Access Memory Bits", by D. W. Westcott, vol. 17, No. 10, Mar. 1975, pp. 2915-2916.
"Microcode Memory Changes", by M. Enser, vol. 21, No. 1, Jun. 1978, pp. 341-342.
"Alterable-Patch Circuits for Read-Only Storage", by J. L. Regehr, vol. 23, No. 10, Mar. 1981, pp. 4627-4628.
"Short and Long ROS Patch", by H. Trinh, vol. 24, No. 3, Aug. 1981; pp. 1379-1382.
"Terminal Microcode Load/Patch Facility", by F. L. Huss et al, vol. 24, No. 10, Mar. 1982, pp. 5273-5274.

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