Data processing apparatus dual-bus data processing with reduced

Details Data processing apparatus dual-bus data processing with reduced Data processing apparatus dual-bus data processing with reduced

1992-05-22

1995-05-02

Ip, Paul

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358437, 358443, G06F 1300

Patent

active

054124883

ABSTRACT:
Disclosed is a data processing apparatus which makes it possible to perform data processing at high speed by efficiently using a plurality of buses with a small number of microprocessors. The apparatus may be realized in the form of a facsimile apparatus including: a first bus connected to a microprocessor; a second bus which is not connected to the microprocessor; a memory connected to both the first and second buses; a memory control section which mediates between memory accesses from these buses so as to allow each of them to use the memory; a group of circuits for performing data processing through the second bus under the control of the microprocessor; and a DMA controller for effecting high-speed data transfer between each of the circuits and the memory.

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