Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2004-12-21
2008-10-07
Malzahn, David H (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
07433911
ABSTRACT:
A data processing apparatus and method are provided for adding n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises determination logic operable to determine the larger operand of the first and second operands, and alignment logic operable to align the n-bit significand of the smaller operand with the n-bit significand of the larger operand. First adder logic is then operable to perform a first sum operation in order to generate a first rounded result in non-redundant form equivalent to the addition of the aligned significands with a rounding increment injected at a first predetermined rounding position appropriate for a non-overflow condition, the first adder logic comprising a single level of adder logic. Further, second adder logic is provided to perform a second sum operation in order to generate a second rounded result in non-redundant form equivalent to the addition of the aligned significands with a rounding increment injected at a second predetermined rounding position appropriate for an overflow condition, the second adder logic also comprising a single level of adder logic. Selector logic is then used to derive the n-bit result from either the first rounded result or the second rounded result.
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Hinds Christopher Neal
Lutz David Raymond
ARM Limited
Malzahn David H
Nixon & Vanderhye P.C.
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