Data processing apparatus and method for making same

Details Data processing apparatus and method for making same Data processing apparatus and method for making same

1995-11-22

1998-06-16

Harrity, John E.

Boots, shoes, and leggings

395308, 3642402, 3642407, 364DIG1, G06F 1340

Patent

active

057686084

ABSTRACT:
A data processing apparatus capable of receiving a CPU of different data bus widths is disclosed. Terminals for the lower 32 bits of a 64-bit data bus and terminals for upper 32 bits of the 64-bit data bus are provided opposing to one another at a connector. Also, terminals for the lower 3 bits of a byte enable signal and terminals for the upper 4 bits of the byte enable signal are disposed opposing one another. When a first CPU module having a 32-bit CPU is installed, a bus connector board is coupled to the connector to couple the corresponding terminals of the lower 32 bits and the upper 32 bits, and the corresponding terminals of the lower 3 bits and the upper 4 bits of the byte enable signal.

REFERENCES:
patent: 5280598 (1994-01-01), Osaki et al.
patent: 5301281 (1994-04-01), Kennedy
patent: 5301296 (1994-04-01), Mohri et al.
patent: 5349693 (1994-09-01), Matsushita

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