Excavating
Patent
1996-12-16
1999-02-09
Lall, Parshotam S.
Excavating
39518203, 39518301, 39518306, 39518507, 395598, 395567, 395568, 371 101, 371 102, G06F 1100
Patent
active
058706011
DESCRIPTION:
BRIEF SUMMARY
The invention relates to a data processing apparatus, a method for storage of microcode and a method for correcting faulty microcode.
The programming language utilized to program microprocessors or processors in general is commonly referred to as assembler language or assembly language. Each individual assembler instruction is referred to as a microinstruction, and each macroinstruction usually consists of a plurality of microinstructions. Microinstructions are the basic or primitive instructions that the microprocessor or processor can perform. The macroinstructions are a higher level language than the microinstructions and typically require several states to complete execution. Depending on the particular microprocessor or processor, the microinstructions required to implement a specific macroinstruction will vary.
A microprocessor or processor system consists basically of three main modules; namely, the microcontrol logic module, the control memory logic module, and the data path module. The two major functional areas of concern are the microcontrol logic module and the control memory logic module. The data path module is responsible for the manipulation of data through the system. The microinstructions are stored in the control memory and are collectively referred to as the system or processor firmware. Each microinstruction consists of a plurality of fields including one field which is used in conjunction with the processor control flags and the operation code of the macroinstruction to determine the next sequential microinstruction to be executed. The other primary field is used to control the data path. The macroinstruction operation code is read by the microcontrol logic and determines which microroutine to execute next.
In high speed processors, the control memory is usually constructed of bipolar read only memories (ROMS) and programmable read only memories (PROMS) and by replacing the particular ROM, the entire macroinstruction set can be changed. In conventional processors, ROM is widely used for implementing an on-chip control store (control memory). As compared with an off-chip control store, this approach eliminates chip-crossing in the critical path and offers a very large data width, both of which are crucial for the high speed performance of the system. ROM is chosen because it has a density which is approximately 10 times better than that of static random access memory (RAM). However, ROM can only be programmed with mask levels during fabrication which becomes a major disadvantage during the system development stage. A simple microcode error can block the whole system development effort for a significant amount of time. It is therefore desirable to detect and correct instructions without having to reprogram to ROM.
U.S. Pat. No. 4,644,539 to Sato discusses a variety of earlier conventional circuit arrangements for processing a fault or an error occurring in a control memory. One such circuit arrangement for the detection and correction of errors associated with incorrect instructions comprises an error detecting circuit and an error correcting circuit together with a control memory loaded with a plurality of microinstructions. The error detecting circuit is for detecting an error of each microinstruction read out of the control memory while the error correcting circuit is for correcting the error to obtain a correct microinstruction. With this structure, each microinstruction is always sent from the control memory through both the error detecting circuit and the error correcting circuit even when an error is not detected by the error detecting circuit. Therefore, an increase of a machine cycle is inevitable.
In another conventional circuit arrangement, the error detection is normally carried out for each microinstruction read out of a control memory by the use of an error detection circuit. An error correction circuit is operated only when an error is detected by the error detection circuit. With this structure, it is possible to shorten the machine cycles as compared with the above-ment
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patent: 5212693 (1993-05-01), Chao et al.
patent: 5483638 (1996-01-01), Katsuta
patent: 5561760 (1996-10-01), Ferris et al.
patent: 5701506 (1997-12-01), Hosotani
Getzlaff Klaus Jorg
Koester Ralph
Mertin Christian
Pflueger Thomas
Tast Hans-Werner
Barot Bharat
Ehrlich Marc A.
International Business Machines - Corporation
Lall Parshotam S.
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