Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-07-28
2003-04-01
Malzahn, David H. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S523000
Reexamination Certificate
active
06542916
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processing apparatus and method for applying floating-point operations to first, second and third operands.
2. Description of the Prior Art
It is common for data processing apparatus to be required to perform various floating-point computations on data. It has been found that general purpose processors are not well suited to the performance of floating-point computations, and hence this has led to the development of specialised floating-point units (FPUs) to handle such computations.
One particular floating-point computation which is commonly required is a multiply-accumulate operation A+(B*C), whereby two numbers are multiplied together, and the product is then added to a third number. Although a multiply-accumulate operation can be performed by executing a multiplication instruction followed by a separate accumulate instruction, such an approach is relatively slow. Hence, there has been a great deal of interest in developing FPUs arranged specifically to perform multiply-accumulate operations with increased speed.
Examples of FPUs designed specifically to increase the speed of a multiply-accumulate operation and/or reduce circuit complexity can be found in U.S. Pat. No. 4,969,118, U.S. Pat. No. 5,241,493, U.S. Pat. No. 5,375,078, U.S. Pat. No. 5,530,663, EP-A-0,645,699, U.S. Pat. No. 4,866,652 and U.S. Pat. No. 4,841,467. Alternatively, the multiplier and adder can be retained as separate logic units.
Another similar floating-point computation often used is a multiply-subtract operation −A+(B*C), which typically can be performed using the same multiply-accumulate logic, but negating the value A before it is input to the adder.
In addition to performing the above multiply-accumulate and multiply-subtract operations, it is desirable to also be able to produce negated versions of the multiply-accumulate and multiply-subtract operations, since such operations are useful in complex multiply routines, Fast Fourier Transform (FFT) and filter routines, and general computations used by a compiler.
Intel describe an instruction for performing a negated version of the multiply-subtract operation in the IA-64 Application Developer's Architecture Guide, Rev 1.0, page 7-59. Here a “floating-point negative multiply add” instruction is defined, where the product of two floating-point register values is computed to infinite precision, negated, and then the value in a third floating-point register is added to the product, again in infinite precision. Rounding is then performed on the final value. Hence, this Intel instruction evaluates the expression A−(B*C).
A standard was produced in 1985 to ensure a consistent approach in the way in which floating-point computations are handled by various data processing apparatus, this standard being called the “IEEE Standard for Binary Floating-Point Arithmetic”, ANSI/IEEE Std 754-1985, The Institute of Electrical and Electronic Engineers, Inc., New York, 10017 (hereafter referred to as the IEEE 754-1985 standard). This standard defined, amongst other things, that a multiplication operation should finish with a rounding operation, and similarly that an add, or accumulate, operation should finish with a rounding operation. The IEEE 754-1985 standard further provided a definition of a number of rounding operations which would be considered to be compliant with the IEEE 754-1985 standard.
In accordance with the above Intel technique, a ‘fused’ multiply-accumulate circuit is used, which results in efficient processing of the above instruction, but means that the result of the multiplication is not independently determined prior to the accumulate operation. Further, the multiplication is performed to an internal precision which contains all of the bits from the multiplication (for an n×n bit multiplication the result is 2n bits) and the accumulation is then performed using all of the multiply bits. Due to this approach, no rounding is performed on the result of the multiplication before that result is used in the subsequent accumulation. Hence, it is apparent that this technique is not compliant with the IEEE 754-1985 standard since that standard defines that a rounding operation should be performed on the result of the multiplication.
Another way of performing negated versions of the multiply-accumulate and multiply-subtract operations would be to perform the multiply-accumulate and multiply-subtract operations as usual and then negate the final result output by the FPU. In this way the negated operations −(A+(B*C)) and −(−A+(B*C) can be performed, and these operations will produce the desired algebraic results.
Indeed, the IBM Power architecture specifies multiply-add with negate functions of the above type. According to the PowerPC 601 RISC Microprocessor User's Manual, (IBM) 52G7484 (MPR601UMU-02) or (MOT) MPC601UM/AD, REV 1, pp. 10-76-10-79, the IBM Power architecture specifies the following four instructions:
fnmaddx: frD=−([(frA)*(frC)]+(frB))
fnmaddsx: (same, but with single precision data)
fnmsubx: frD=−([(frA)*(frC)]−(frB))
fnmsubsx: (same, but with single precision data)
Like Intel's approach, IBM used a fused multiply-accumulate unit, and so also cannot guarantee results which are compliant with the IEEE 754-1985 standard.
The MIPS IV architecture also defines two instructions which perform multiply-add negate functions similar to the IBM instructions, the instructions being as follows:
NMADD.fmt: fd=−((fs*ft)+fr)
NMSUB.fmt: fd=−((fs*ft)−fr)
The description on pages B-78 to B-79 of the “MIPS IV Instruction Set”, Revision 3.2, September 1995, by Charles Price, reads as follows: “The value in fs is multiplied by the value in FPR ft to produce an intermediate product. The value in FPR fr is added to/subtracted from the product. The result sum is calculated to infinite precision, rounded according to the current rounding mode in FCSR, negated by changing the sign bit, and placed in FPR fd.”
Since the MIPS architecture retains the multiplier and adder as separate logic units, then when performing a multiply-accumulate operation, rounding is applied to the output of the multiplier unit, and this output is then input to the adder logic unit, with the result of the adder logic unit also being rounded. Hence, this enables an IEEE 754-1985 compliant result to be achieved for the expressions −(−A+(B*C)) and −(A+(B*C)).
Further, it will be appreciated that the formula −(−A+(B*C)) is mathematically equivalent to the formula A−(B*C), and similarly the formula −(A+(B*C)) is mathematically equivalent to the formula −A−(B*C), and so instructions of the type as used by MIPS can be used to produce the correct mathematical results for the expressions A−(B*C) or −A−(B*C).
SUMMARY OF THE INVENTION
Viewed from a first aspect, the present invention provides a data processing apparatus for applying a floating-point multiply-accumulate operation to first, second and third operands, comprising: a multiplier for multiplying the second and third operands and applying rounding to produce a rounded multiplication result; an adder for adding the rounded multiplication result to the first operand to generate a final result and for applying rounding to generate a rounded final result; and control logic, responsive to a first single instruction, to control the multiplier and adder to cause the rounded final result generated by the adder to be equivalent to the subtraction of the rounded multiplication result from the first operand.
The present invention realises that although the above-mentioned prior art instructions for performing the computation −(−A+(B*C)) enable the correct mathematical results to be obtained for the formula A−(B*C), those prior art instructions will not produce the correctly signed results f
Hinds Christopher Neal
Jaggar David Vivian
Seal David James
Arm Limited
Malzahn David H.
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