Electrical computers and digital processing systems: processing – Instruction fetching
Reexamination Certificate
1997-08-05
2001-02-13
Treat, William M. (Department: 2783)
Electrical computers and digital processing systems: processing
Instruction fetching
C711S214000, C711S215000, C711S219000, C711S220000
Reexamination Certificate
active
06189086
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processing apparatus which processes data as a result of executing a program including predetermined instructions, for example, to a CPU such as a microprocessor and a computer using a CPU.
2. Description of the Related Art
In a data processing apparatus such as a microprocessor, instructions of a program are executed one by one. Thus, data processing is performed. At this time, data on which an operation indicated by an instruction to be executed is to be performed is taken from a main memory as an operand. Ordinarily, an address is allocated in the main memory for each byte. When an operand is taken out, the address indicates the position of the main memory at which the operand is stored. For a microprocessor or the like, several addressing modes are prepared as address indicating methods. For example, in an absolute addressing mode an address is directly indicated by code data included in an instruction. In a displacement-adding register indirect addressing mode, an address is obtained as a result of a displacement being added to a value stored in a predetermined register. The displacement is indicated by an instruction. Each instruction included in a program for data processing includes data (hereinafter, referred to as ‘addressing data’) which indicates the address of an operand of the instruction.
The size of a program used for performing data processing in a microprocessor or the like is a large factor to determine evaluation of the microprocessor or the like. It is preferable that the size of a program required for a desired data processing is shorter. For this purpose, it is demanded to reduce the size of the above-mentioned addressing data included in each instruction of a program. However, by simply reducing the size of the addressing data, a range of addresses which can be indicated is reduced. Thereby, data which can be processed is limited, and flexibility of programing is degraded.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a data processing apparatus such as a microprocessor or the like in which, without reducing a range of addresses which can be indicated, a program size can be reduced.
A first data processing apparatus according to the present invention executes a program including an instruction which indicates an address for taking out an operand from a main memory in a predetermined addressing mode which belongs to a displacement-adding register indirect addressing mode. The first data processing apparatus comprises:
address generating means for shifting by a predetermined number of bits the value of the displacement which is indicated by the instruction, adding the thus-shifted value to the value stored in a predetermined register and thus generating an effective address, when the operand of the instruction is taken out from the main memory.
A second data processing apparatus is the data processing apparatus according to the first data processing apparatus. In the second data processing apparatus, the address generating means treats the value of the displacement as a positive integer without sign and performs the shifting and the adding.
A third data processing apparatus is the data processing apparatus according to the first data processing apparatus. In the third data processing apparatus, the address generating means treats the value of the displacement as a negative integer without sign and performs the shifting and the adding.
A fourth data processing apparatus is the data processing apparatus according to the first data processing apparatus. In the fourth data processing apparatus, the address generating means adds the shifted value of the displacement to the value stored in a register which is previously fixed for the addressing mode of the instruction and thus generates the effective address.
A fifth data processing apparatus is the data processing apparatus according to the third data processing apparatus. The fifth data processing apparatus further comprises an FP register which stores the value of a frame pointer. In the fifth data processing apparatus, the address generating means treats the value of the displacement indicated by the instruction as an integer without sign, shifts the value one bit leftwardly, causes the resulting value to be a negative integer by adding ‘1’ as the sign bit to the value as the most significant bit, adds the negative integer to the value stored in the FP register and thus generates the effective address.
A sixth data processing apparatus is the data processing apparatus according to the fourth data processing apparatus. In the sixth data processing apparatus:
the instruction includes a 2-bit field for indicating any of three sizes as the size of the operand of the instruction; and
the address generating means adds the shifted value of the displacement to the value stored in the register which is previously fixed for the addressing mode of the instruction and thus generates the effective address, when a value of the four values which can be expressed by the 2 bits, the value not being used for indicating the size of the operand, is set in the 2-bit field.
A seventh data processing apparatus according to the present invention executes a program including an instruction which indicates an address for taking out an operand from a main memory in a predetermined addressing mode which belongs to an absolute addressing mode. The seventh data processing apparatus comprises:
address generating means for shifting by a predetermined number of bits the value of the address which is indicated by the instruction, the thus-shifted value being used as an effective address, when the operand of the instruction is taken out from the main memory.
In the first data processing apparatus according to the present invention, in the displacement-adding register indirect addressing mode, when the value of each displacement is a multiple of 2 or a multiple of 4 because data of operands is arranged from addresses of multiples of 2 or addresses of multiples of 4, an addressing mode is used in which the data obtained from removing the less significant 1 bit or 2 bits from the displacement is used as the displacement, and the effective address can be generated as a result of the value of the displacement being shifted leftwardly 1 bit or 2 bits. Accordingly, in the above-described case of the displacement-adding register indirect addressing mode, it is possible to reduce the length of the instruction. Generally speaking, the size of each operand is an integer times the length of the basic word of the data processing apparatus, and, in many cases, data of operands is arranged from addresses of multiples of 2 or multiples of 4. Accordingly, by using this data processing apparatus, it is possible to reduce the size of a program to be executed.
In the second data processing apparatus according to the present invention, in the displacement-adding register indirect addressing, when the displacement is a positive integer, it is possible to use an addressing mode in which the integer without sign is used as the displacement, and the effective address can be obtained as a result of the integer without sign being shifted the predetermined number of bits and the resulting value being added to the value of the predetermined register. Accordingly, in the above-described case of the displacement-adding register indirect addressing mode, it is possible to further reduce the length of the instruction. Thereby, by using the second data processing apparatus, it is possible to further reduce the size of a program to be executed.
In the third data processing apparatus according to the present invention, in the displacement-adding register indirect addressing, when the displacement is a negative integer, it is possible to use an addressing mode in which the integer without sign is used as the displacement, and the effective address can be obtained as a result of the integer without sign being shifted the predetermined number of bits and the
Cooper & Dunham LLP
Ricoh & Company, Ltd.
Treat William M.
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