1997-11-03
1999-09-14
Heckler, Thomas M.
395880, G06F 1338
Patent
active
059535210
ABSTRACT:
The amount of skew present in a signal delivered over a transmission line is reduced by identifying of the type of data pattern from which a bit of data is being sent and generating a corresponding delay in response to identification of the data pattern is described. The generated delay results in reducing the amount of skew present in the system. In a first configuration, the invention includes first-storage and second-storage mechanisms, a logic gate, first and second delay paths, and a mechanisms for generating an output terminal. The first-storage mechanism stores a first digital signal. The second-storage mechanism stores a second digital signal that occurs in a selected number of clock transitions after the first data signal. The two storage mechanisms are connected to a logic gate. The first storage mechanism is also connected to the first and second delay paths which delay signals sent to them. A generating mechanism is connected to the delay paths and the logic gate and generates an output terminal signal in response to the selection of a digital signal from either the first or second delay path. A second configuration includes bypass circuitry coupled to the generating mechanism and the logic device.
REFERENCES:
patent: 5101347 (1992-03-01), Balakrishnan et al.
patent: 5426772 (1995-06-01), Brady
patent: 5502819 (1996-03-01), Aldrich et al.
Dabral Sanjay
Sampath Dilip K.
Heckler Thomas M.
Intel Corporation
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