Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2008-10-30
2010-12-14
Tran, Michael T (Department: 2827)
Static information storage and retrieval
Floating gate
Multiple values
C365S185240
Reexamination Certificate
active
07852671
ABSTRACT:
Memories, data paths, methods for storing, and methods for utilizing are disclosed, including a data path for a memory using multi-level memory cells to provide storage of multiple bits per memory cell. One such data path includes a bit mapping circuit and a data converter circuit. Such a bit mapping circuit can be configured to map bits of the original data to an intermediate arrangement of bits and such a data converter circuit can be configured to receive the intermediate arrangement of bits and convert the intermediate arrangement of bits into intermediate data corresponding to a memory state to be stored by memory cells of a memory cell array.
REFERENCES:
patent: 5473577 (1995-12-01), Miyake et al.
patent: 5771248 (1998-06-01), Katayama et al.
patent: 6483742 (2002-11-01), Sweha et al.
patent: 6512525 (2003-01-01), Capps et al.
patent: 6532556 (2003-03-01), Wong et al.
patent: 7278723 (2007-10-01), Silverbrook
patent: 2003/0081693 (2003-05-01), Raghavan et al.
patent: 2007/0171714 (2007-07-01), Wu et al.
patent: 2007/0195597 (2007-08-01), Park et al.
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Tran Michael T
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