Data path chip test architecture

Details Data path chip test architecture Data path chip test architecture

1988-06-13

1990-05-29

Eisenzopf, Reinhard J.

Excavating

371 251, G01R 3126

Patent

active

049298895

ABSTRACT:
A system and method for testing nodes, or test points, of an integrated circuit are presented. The invention includes a test/load bus which is used to sequentially load test data and other data onto the integrated circuit chip, to sample test points and to read data previously loaded onto the chip. The test/load bus and its control logic are used for both testing the chip and for loading and dumping data from the chip so that the test capability adds little to the area of the chip.

REFERENCES:
patent: 4493078 (1985-01-01), Daniels
patent: 4577318 (1986-03-01), Whitacre et al.
patent: 4631724 (1986-12-01), Shimizu
patent: 4635261 (1987-01-01), Anderson et al.
patent: 4749947 (1988-06-01), Gheewala
Built-In Test for VLSI: Pseudorandom Techniques, by Paul H. Bardell, William H. McAnney and Jacob Savir; International Business Machines Corporation; John Wiley & Sons, New York, 1987.

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