Data path architecture for a LAN switch

Details Data path architecture for a LAN switch Data path architecture for a LAN switch

1998-01-30

2001-09-25

Chin, Wellington (Department: 2664)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S428000

Reexamination Certificate

active

06295299

ABSTRACT:

COPYRIGHT NOTICE
Contained herein is material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction of the patent disclosure by any person as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all rights to the copyright whatsoever.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of Local Area Network (LAN) switching. In particular, the present invention relates to a scaleable data path architecture and a data comparison engine utilized in filtering and forwarding data packets by a LAN switch operating in high speed LANs such as a Gigabit Ethernet LAN.
2. Description of the Related Art
Initial, or first generation, LAN switches solved congestion problems associated with traditional LANs that arose as workgroups and networks, such as an Ethernet (operating at 10 million bits per second (10 Mb/s)), grew. (The term Ethernet LAN, or simply Ethernet, as used herein shall apply to LANs adhering to the Carrier Sense, Multiple Access with Collision Detection (CSMA/CD) standard, generally operating at a signaling rate of 10 Mb/s over various media types and transmitting Ethernet formatted or Institute of Electrical and Electronic Engineers (IEEE) standard 802.3 formatted data packets). Adding new users and deploying new applications required more bandwidth (i.e., data transfer capability as that term is applied to networks) than Ethernet LANs could reasonably provide. The result was slow performance primarily due to network congestion. Initial Ethernet switches reduced the congestion by segmenting workgroups into different LANs having separate collision domains and switching traffic, i.e., data packets, between the workgroups at very high speeds.
Deployment of first generation Ethernet switches and growth of the client/server computing model moved the primary network performance bottleneck from the end station to the Ethernet switch port connected to, for example, a high-performance server. Second generation Ethernet switches added a port connected to a relatively high-speed communications medium, commonly referred to as a backbone. Connecting a port on the Ethernet switch to a backbone operating according to a high-speed technology such as Fiber Distributed Data Interface (FDDI), Asynchronous Transfer Mode (ATM), or Fast Ethernet, opened up the bottleneck allowing traffic from many clients connected to the Ethernet switch to be switched efficiently at the connection to the server or backbone. (The term Fast Ethernet LAN, or simply Fast Ethernet, as used herein shall apply to LANs adhering to the Carrier Sense, Multiple Access with Collision Detection (CSMA/CD) standard, generally operating at a signaling rate of 100 Mb/s over various media types and transmitting Ethernet formatted or Institute of Electrical and Electronic Engineers (IEEE) standard 802.3 formatted data packets).
Until recently, network traffic patterns in the client/server network model were generally predictable. Most traffic remained on a local LAN as clients accessed local servers. Occasionally, a small percentage of traffic, for example, electronic mail, went outside the workgroup connected to a common shared communications medium. Today, intranet, Internet, and World Wide Web (WWW) communication have significantly changed traffic patterns. Data can now exist and be randomly accessed anywhere, in contrast to the traffic patterns in traditional client/server networks. Additionally, more powerful applications and computers capable of providing, for example, video and multimedia at the desktop end station are driving the need for greater network speed and bandwidth.
Signaling rates associated with very high-speed technologies such as Gigabit Ethernet and the rapid assimilation of more powerful applications and computers relying on intranet or Internet communication have driven the need for next generation of LAN switches. (The term Gigabit Ethernet LAN, or simply Gigabit Ethernet, as used herein shall apply to LANs adhering to the Carrier Sense, Multiple Access with Collision Detection (CSMA/CD) standard, generally operating at a signaling rate of 1,000 Mb/s over various media types and transmitting Ethernet formatted or Institute of Electrical and Electronic Engineers (IEEE) standard 802.3 formatted data packets).
What is needed is a highly scaleable LAN switch capable of resolving today's congestion problems, handling delay-sensitive and real-time data, scaling network size to support thousands of users, and aggregating the different speeds of traffic through the network. A third generation LAN switch extends the evolutionary migration from 10 Mb/s CSMA/CD (Ethernet) to 100 Mb/s CSMA/CD (Fast Ethernet) to 1,000 Mb/s CSMA/CD (Gigabit Ethernet) backbones. Such network scalability is important to LAN design and migration, allowing optimization of the network by providing high-speed links for trunking and server connections while maintaining performance at the desktop.
Thus, third generation LAN switches should be capable of providing sufficient bandwidth within the switch to remove any possibility of contributing to network congestion. The switch should be capable of switching multiple high-speed and low-speed ports simultaneously without any blocking throughput on any port. Furthermore, the switch should guarantee full bandwidth availability at all times. The switch capacity, in particular, the backplane capacity of the switch, should be greater than the sum of all its ports so data packets are never dropped or lost even when the network load requires all ports to support, for example, full-duplex gigabit bandwidth. Additionally, the switch should be capable of bridging (at the Media Access Control (MAC) layer) or routing (at the Network layer) data packets at least as fast as the data transmission speed of the communication media to which it is attached.
Various third generation LAN switch architectures have several key differences in LAN switch implementations. For example, a so-called Gigabit Ethernet switch may simply utilize a number of Fast Ethernet ports, e.g., 6 Fast Ethernet ports, and include a single Gigabit Ethernet port. Such a switch needs only to provide internal bandwidth capacity somewhere in the range of 1-2 gigabits per second, which is generally within the capability of any LAN switch, regardless of the switch architecture, but fails to provide the desired scalability referred to above or guaranteed bandwidth availability.
What is needed is a switch architecture that readily supports multiple Fast Ethernet ports and/or a number of Gigabit Ethernet ports, for example, 64 Fast Ethernet ports, or 8 Gigabit Ethernet ports, or a combination thereof. Traditional LAN switch architectures, such as central shared memory-, cross-bar switch-, or bus-based architectures generally have a maximum internal bandwidth capability of 2 Gigabits per second (Gb/s). 2 Gb/s bandwidth appears to be a threshold above which scaling such traditional switch architectures is generally not feasible. Thus, given a LAN switch having, for example, 8 Gigabit Ethernet ports, these traditional architectures are generally incapable of providing sufficient bandwidth within the switch to remove any possibility of contributing to network congestion, switching multiple high-speed and low-speed ports simultaneously without any blocking throughput on any port, and providing full bandwidth availability at all times.
As an example, some prior art bus-based switches have utilized a backplane bus operating according to the well known Peripheral Component Interconnect (PCI) local bus standard. The PCI bus can exchange data at either 32 or 64 bits per clock cycle, depending on the implementation. Operating at a speed of 33 MHz, a 32-bit wide PCI bus is therefore generally capable of achieving 1 Gb/s bandwidth, while a 64-bit wide PCI bus is generally capable of achieving 2 Gb/s bandwidth. Scaling the clock speed of the PCI bus to 66 MHz to achieve a bit rate of 4 Gb/s is possible, but is generally

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