Data oversampling via clock and data interpolation

Details Data oversampling via clock and data interpolation Data oversampling via clock and data interpolation

2008-04-01

2008-04-01

Payne, David C. (Department: 2611)

Pulse or digital communications

Cable systems and components

C327S141000, C327S165000, C348S538000, C365S242000, C370S395620, C375S371000, C375S373000, C398S155000

Reexamination Certificate

active

07352816

ABSTRACT:
An oversampling delay is provided between clock and data signals by steering a current between first and second nodes. The first node is coupled to an input differential pair of a clock interpolator and a delayed differential pair of a data interpolator. The second node is coupled to an input differential pair of the data interpolator and a delayed differential pair of the clock interpolator. First clock and data signals are provided to a first data sampling element and, respectively, to the clock and data interpolators. Second clock and data signals, respectively output from the clock and data interpolators, are provided to a second data sampling element. Additional data sampling elements may be linked to form a longer chain of data sampling elements.

REFERENCES:
patent: 5012494 (1991-04-01), Lai et al.
patent: 6002279 (1999-12-01), Evans et al.
patent: 2001/0053187 (2001-12-01), Simon et al.
patent: 2003/0002607 (2003-01-01), Mooney et al.

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