Data output clock selection circuit for quad-data rate...

Details Data output clock selection circuit for quad-data rate... Data output clock selection circuit for quad-data rate...

2008-07-15

2008-07-15

Whitmore, Stacy (Department: 2825)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C716S030000, C713S400000, C326S093000, C714S814000

Reexamination Certificate

active

11278368

ABSTRACT:
A method for selecting a data output clock signal includes providing a complementary output clock signal pair to a combinational logic circuit, thereby generating a reset control signal. The reset control signal is activated if the complementary output clock signals have different values, and deactivated if these clock signals have the same predetermined value. The activated reset control signal asynchronously resets a pair of series connected flip-flops. The deactivated reset control signal enables the flip-flops to synchronously propagate a fixed logic signal in response to a clock signal of a complementary input clock signal pair. The output signal of the series-connected flip-flops is used to select the data output clock signal from the first complementary clock signal pair and the second complementary clock signal pair.

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