Data output circuit with reduced output noise

Details Data output circuit with reduced output noise Data output circuit with reduced output noise

2000-11-09

2002-09-03

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S112000, C326S087000

Reexamination Certificate

active

06445222

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to output circuits, and more particularly, to improvement of a data output circuit used in a semiconductor memory device.
2. Description of the Background Art
FIG. 86
is a block diagram schematically showing an entire structure of a general dynamic semiconductor memory device. Referring to
FIG. 86
, the dynamic semiconductor memory device includes a memory cell array
900
in which dynamic type memory cells MC are arranged in a matrix of rows and columns. In memory cell array
900
, a word line WL is provided corresponding to each row of memory cells. A pair of bit lines BL and ZBL are provided corresponding to each column of memory cells MC. A memory cell MC is provided corresponding to the crossing of one word line WL and a pair of bit lines BL and ZBL.
FIG. 86
representatively shows one word line WL and a pair of bit lines BL and ZBL. Data complementary to each other appear on bit line BL and complementary bit line ZBL.
The dynamic semiconductor memory device further includes an address buffer
902
for generating internal row and column address signals RA and CA according to an externally applied address signal Ad, a row decoder
904
for decoding an internal row address signal RA from address buffer
902
to select a corresponding word line in memory cell array
900
, and a column decoder
906
for decoding an internal column address signal CA from address buffer
902
to generate a column select signal for selecting a corresponding column (bit line pair) in memory cell array
900
.
Address buffer
902
includes a row latch
905
activated in response to an internal row address strobe signal ZRAS for latching an applied address signal Ad and generating an internal row address signal RA, and a column latch
907
responsive to an internal column address strobe signal ZCAS for latching an applied address signal Ad and generating an internal column address signal CA.
A row address signal and a column address signal are provided to address buffer
902
in a time-division multiplexed manner. Internal row address strobe signal ZRAS is generated from RAS buffer
910
receiving an external row address strobe signal /RAS. Internal column address strobe signal ZCAS is generated from CAS buffer
912
activated in response to activation of internal row address strobe signal ZRAS and receiving an external column address strobe signal /CAS.
The dynamic semiconductor memory device further includes a sense amplifier
914
for detecting and amplifying data of a memory cell connected to a word line selected in memory cell array
900
, and an IO gate
916
responsive to the column select signal from column decoder
906
for connecting a corresponding column (a bit line pair) in memory cell array
900
to an internal data bus
915
. Sense amplifier
914
has its operation controlled by a clock control circuit
918
responsive to internal row address strobe signal ZRAS for generating a sense amplifier activation signal (not shown explicitly) at a predetermined timing. Clock control circuit
918
also controls the activation/inactivation of row decoder
904
.
The semiconductor memory device further includes an ATD circuit
920
for detecting a change in internal column address signal CA from column latch
907
for generating an address transition detection signal &phgr;ATD when the change is detected, an input/output control circuit
922
for generating a timing control signal determining data input/output timing according to internal column address strobe signal ZCAS from CAS buffer
912
, an external write/read designating signal (write enable signal) /WE, and address transition detection signal &phgr;ATD, an input circuit
924
responsive to a data write designating signal (not explicitly shown) from input/output control circuit
922
for transmitting internal write data according to external data D to internal data bus
915
, and an output circuit
926
responsive to a data output permission signal from input/output control circuit
922
for generating and providing external readout data Q from the internal readout data appearing on internal data bus
915
.
Write enable signal /WE specifies a data writing operation when attaining an L level (logical low), and a data readout operation when attaining an H level (logical high). The operation will now be described briefly.
When external row address strobe signal /RAS is pulled down to an L level, which in turn causes internal row address strobe signal ZRAS from RAS buffer
910
to attain an L level, a memory cycle is initiated. In response to internal row address strobe signal ZRAS attaining an L level, row latch
904
in address buffer
902
latches a currently applied address signal Ad to generate and provide to row decoder
904
an internal address signal RA. Clock control circuit
918
provides an activation signal to row decoder
904
according to this internal row address strobe signal ZRAS at L level. Row decoder
904
decodes internal row address signal RA to select a corresponding word line in memory cell array
900
. As a result, data in a memory cell connected to the selected word line is read out on a corresponding bit line BL (or ZBL). Then, sense amplifier
914
is activated according to a sense amplifier activation signal (not explicitly shown) from clock control circuit
918
, whereby the potentials on bit lines BL and ZBL are amplified differentially.
Following the fall of external row address strobe signal /RAS, external column address strobe signal /CAS attains an L level, and internal column address strobe signal ZCAS of an L level is generated from CAS buffer
912
attaining an enable state by internal row address strobe signal ZRAS of an L level. In response to internal column address strobe signal ZCAS, column latch
907
latches an applied address signal Ad to generate an internal column address signal CA. Column decoder
906
decodes this internal column address signal CA to generate a signal for selecting a column (a bit line pair) in memory cell array
900
. Following the sensing and amplification of memory cell data on each bit line pair by sense amplifier
914
, IO gate
916
responds to a column select signal from column decoder
906
to conduct, whereby a corresponding bit line pair is connected to internal data bus
915
. Then, data writing or reading is carried out via input circuit
924
or output circuit
926
.
FIG. 87
shows a structure of a 1-bit data output unit of output circuit
926
. When the semiconductor memory device of
FIG. 86
has a structure where multibit data such as 4 bits and 8 bits are input/output, a plurality of the input/output units of
FIG. 87
are provided according to the number of bits of data.
Referring to
FIG. 87
, output circuit
926
includes an inverter
5
for inverting data ZDD appearing on an internal data bus line
915
b,
a 2-input AND gate
3
receiving an output permission signal OEM and an output of inverter
5
, a 2-input AND circuit
4
receiving output permission signal OEM and internal readout data ZDD, a first output drive transistor
1
responsive to an output of AND circuit
3
for driving an output node
6
to a level of a power supply potential Vcc, and a second drive transistor
2
responsive to an output of AND circuit
4
for discharging output node
6
to the level of a ground potential GND. Drive transistors
1
and
2
are both formed of an n channel MOS (insulated gate type) transistor. Output permission signal OEM is generated according to internal column address strobe signal ZCAS from input/output control circuit
922
shown in FIG.
86
and address transition detection signal &phgr;ATD. The operation of the output circuit shown in
FIG. 87
will now be described with reference to the operation waveform diagram of FIG.
88
.
At an elapse of a predetermined time period from the attaining of internal column address strobe signal ZCAS to L level, a signal of a logic opposite to that of data in the selected memory cell is transmitted on internal data bus line
915
b
.

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