Data output circuit with means for preventing more than half the

Details Data output circuit with means for preventing more than half the Data output circuit with means for preventing more than half the

1984-05-16

1986-05-06

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307200A, 307242, 307262, 307464, 307465, 307475, 307480, 328110, 328118, H03K 1716, H03K 19003

Patent

active

045874450

ABSTRACT:
A data output circuit provided with data input terminals to which n-bit logic data is supplied, a latching section for holding this logic data, and output buffers for outputting in parallel the logic data held in the latching section.
The data output circuit further includes exclusive OR gates for detecting the non-coincidence between each of 1-bit signals applied from the data input terminals and its corresponding one of 1-bit output signals applied from the latching section; a majority circuit for generating an inversion control signal in response to the non-coincidences whose number is larger than n/2; and a circuit for generating a logic notation signal, synchronized with the data held in the latching section. The latching section holds the inverted replica of logic signals applied from the data input terminals in response to the inversion control signal.

REFERENCES:
patent: 3666968 (1972-05-01), Krocheski et al.
patent: 4044312 (1977-08-01), D'Ortenzio
patent: 4063174 (1977-12-01), Gupta et al.
patent: 4342065 (1982-07-01), Larson
patent: 4398101 (1983-08-01), Friauf
patent: 4475049 (1984-10-01), Smith et al.
patent: 4481427 (1984-11-01), Suzuki et al.
Gani et al., "Bilevel Line Driver and Receiver", IBM T.D.B., vol. 17, No. 6, Nov. 1974, pp. 1616-1617.

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