Data output circuit for reducing skew of data signal

Details Data output circuit for reducing skew of data signal Data output circuit for reducing skew of data signal

2003-06-30

2004-11-23

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C326S082000

Reexamination Certificate

active

06822490

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data output circuit, and more particularly, to a data output circuit by which, if an output voltage level is different from an operating voltage level, the difference is detected, and consequently the skew of an output data signal is controlled.
2. Description of the Related Art
As semiconductor devices evolve, they continue to consume a large amount of power while, at the same time, continue to demand high-speed operation. Accordingly, methods for reducing power consumption have been proposed, including the commonly used approach of lowering the operating voltage level.
Hence, in a single semiconductor device, circuits that interface with each other may use different voltage sources. In particular, a voltage source for operating the internal circuit of a semiconductor device may be different from a voltage source for an output driver circuit that outputs a data signal.
FIG. 1
is a circuit diagram of a conventional data output circuit that utilizes first and second operating voltage levels that are different. Referring to
FIG. 1
, a conventional data output circuit
100
includes a buffer logic unit
110
, a pre-driver unit
120
, and a main driver unit
130
.
The buffer logic unit
110
buffers a data signal DATA and an inverted data signal DATA for a predetermined period of time in response to a clock signal CLK to obtain first and second data signals DATA
1
and DATA
2
. To perform this operation, the buffer logic unit
110
includes transmission gates
111
and
113
and inverters I
1
, I
2
, I
3
, I
4
, and I
5
.
The buffer logic unit
110
can further include an NMOS transistor MN
2
and resistors R
1
and R
2
for controlling skew of the second data signal DATA
2
in response to a comparison voltage signal VCOM. Generation of the comparison voltage signal VCOM is described below with reference to FIG.
2
.
Power for the buffer logic unit
110
is supplied according to the operating voltage level of.the internal circuit (not shown) of the data output circuit
100
.
The pre-driver unit
120
converts the first and second data signals DATA
1
and DATA
2
, which have an operating voltage level, into first and second driving signals DRV
1
and DRV
2
, which have the output voltage level. The logic levels of the first and second data signals DATA
1
and DATA
2
are opposite to those of the first and second driving signals DRV
1
and DRV
2
.
To perform the above operation, the pre-driver unit
120
includes NMOS transistors MN
0
and MN
1
and PMOS transistors MP
0
and MP
1
, which are coupled between a first power supply voltage VDDQ and a first ground voltage VSSQ, which both have the output voltage level.
The main driver unit
130
outputs an output data signal DATAOUT in response to the first and second driving signals DRV
1
and DRV
2
. To achieve this, the main driver unit
130
includes an NMOS transistor MN
3
and a PMOS transistor MP
3
, which are coupled between a first power supply voltage VDDQ and a first ground voltage VSSQ, which both have the output voltage level.
The power for the buffer logic unit
110
of the conventional data output circuit
100
is supplied at a power supply voltage having the operating voltage level for operating the internal circuit (not shown) of the conventional data output circuit
100
. Generally, the power supply voltage has a voltage level of 3.3V or 2.5V.
Both the pre-driver unit
120
and the main driver unit
130
have a first power supply voltage VDDQ and a first ground voltage VSSQ, which both have an output voltage level. The output voltage level is normally the same as an operating voltage level, but in recent trends the output voltage level is becoming lower than the operating voltage level when considering the need for high-speed operation and low power consumption in the output process.
In the conventional data output circuit
100
, when the output voltage level used in the pre-driver unit
120
and the main driver unit
130
is different from the operating voltage level, the inclinations of the first and second driving signals DRV
1
and DRV
2
of the pre-driver unit
120
are changed, and consequently the output data signal DATAOUT is skewed.
In order to prevent skewing, the data output circuit
100
activates the comparison voltage signal VCOM and shortens the time required to transfer the second driving signal DRV
2
to a high level by using a turn-on resistor of the NMOS transistor MN
2
rather than the second resistor R
2
.
The comparison voltage signal VCOM may be automatically generated by detecting a change in the level of the first power supply voltage VDDQ with an output voltage level, or may be set through a mode register setting (MRS) process upon power-up of the circuit, or may be pre-programmed in a fuse-cutting procedure, for example.
FIG. 2
is a circuit diagram of a circuit for automatically generating the comparison voltage signal of FIG.
1
. Referring to
FIG. 2
, an appropriate reference potential for a second power supply voltage VDD with an operating voltage level is generated using the ratio of resistances RA and RB. The reference potential is compared with the first power supply voltage VDDQ having the output voltage level in comparator
210
.
If the level of the first power supply voltage VDDQ is equal to or less than a predetermined voltage level, a comparative voltage signal VCOM at an active, or high, level is generated at inverter
220
.
However, the conventional method of
FIG. 2
of automatically sensing a change in the first power supply voltage VDDQ has a problem in that the reference potential itself may be changed since the resistors RA and RB are sensitive to process change and the voltage level of the second power supply voltage VDD may vary, for example, by ±0.3V.
The method of
FIG. 1
of changing the turn-on resistance of the NMOS transistor MN
2
by activating the comparison voltage signal VCOM also has some problems in that the turn-on resistance of the NMOS transistor MN
2
cannot be zero and can vary as a result of variation in the voltage level of the comparison voltage signal VCOM that is made depending on the voltage level of the second power supply voltage VDD.
In order to activate the output data signal DATAOUT of
FIG. 1
, the first driving signal DRV
1
must have a low level, or the second driving signal DRV
2
must have a high level.
In order to achieve this, the level of the first data signal DATA
1
of
FIG. 1
must be high so that a voltage Vgs between the gate and source of the NMOS transistor MN
0
is VDD-VSSQ. Alternatively, the level of the second data signal DATA
2
of
FIG. 1
must be low so that a voltage Vgs between the gate and source of the PMOS transistor MP
1
is VDDQ-VSS.
However, if the voltage level of the first power supply voltage VDDQ changes, the voltage Vgs between the gate and source of the NMOS transistor MN
0
does not change, however, the voltage Vgs between the gate and source of the PMOS transistor MP
1
changes according to the voltage level of the first power supply voltage VDDQ.
Consequently, when the level of the first power supply voltage VDDQ is low, the voltage Vgs between the gate and source of the PMOS transistor MP
1
is reduced. Thus, the slope of the second driving signal DRV
2
becomes more gradual, and, as a result, the output data signal DATAOUT becomes additionally skewed.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a data output circuit by which, in the case where an output voltage level is different from an operating voltage level, a variation in the output voltage level is detected, and consequently the skew of the output data signal is controlled.
According to a first aspect of the present invention, there is provided a data output circuit including first and second inversion units, first and second voltage compensation units, and a driver unit. The first inversion unit receives a first data signal of an operating voltage level and inverts the received first data signal to obtain a first inverted da

Affiliated with

Also associated with

Rating

Data output circuit for reducing skew of data signal does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data output circuit for reducing skew of data signal, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data output circuit for reducing skew of data signal will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3282329