Data output buffer

Details Data output buffer Data output buffer

2002-06-24

2004-04-13

Nguyen, Long (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S112000, C327S391000, C326S083000

Reexamination Certificate

active

06720802

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
A data output buffer and, more particularly, to a data output buffer capable of reducing the power consumption of a circuit is disclosed that uses low power, by turning off a data output buffer driver to make output data become a HIGH impedance in a deep power down mode.
2. Description of the Related Art
Generally, in memory devices such as DRAM, a data signal of a cell amplified by a bit line sense amplifier in a row address path is transmitted from a bit line to a data bus line when a column select signal outputted from a column decoder turns on a data bus line gate. Then, if the data is inputted to a data bus line sense amplifier, the data bus line sense amplifier is activated to amplify the data again and sends the data to a read driver. Only a read driver selected to a bit combination of the data output is activated so that data is transmitted to a data output buffer. The data output buffer is activated under the control of an output enable signal (OE: output enable) and a /CAS signal. The output path for the data is called a ‘read path’. Of this output path, a dual data output buffer will be described in detail with reference to FIG.
1
.
FIG. 1
is a circuit diagram of a conventional data output buffer.
The conventional data output buffer includes a driver driving control unit
10
for controlling an output of a data output driver
20
. The data output driver
20
transmits read data to a data output terminal according to a control signal from the driver driving control unit
10
.
The driver driving control unit
10
includes a first level shifter
11
and a first output control unit
12
. First, the first level shifter
11
includes PMOS transistors P
1
and P
2
having a cross coupled structure and NMOS transistors N
1
and N
2
receiving an output enable signal OE and an output enable signal /OE inverted by an inverter IV
1
, respectively. Also, the first output control unit
12
includes an inverter IV
2
for inverting an output control signal DOFFZ outputted from the first level shifter
11
to produce an output control signal DOFF.
The data output driver
20
includes a second level shifter
21
, a third level shifter
22
, a first pull-up control unit
23
, a first pull-down control unit
24
and a first output driver
25
. First, the second level shifter
21
includes PMOS transistors P
3
and P
4
, NMOS transistors N
3
and N
4
, and NMOS transistor N
5
. PMOS transistors P
3
and P
4
have a cross coupled structure, NMOS transistors N
3
and N
4
receive a data signal RDO and an inverted data signal /RDO inverted by an inverter IV
3
, and NMOS transistor N
5
controls the output of the data signal RDO depending on the input of a pipe counter signal PCNT.
Also, the third level shifter
22
includes PMOS transistors P
5
and P
6
, NMOS transistors N
6
and N
7
, and NMOS transistor N
8
. PMOS transistors P
5
and P
6
have a cross coupled structure, NMOS transistors N
6
and N
7
receive the data signal RDO and an inverted data signal /RDO inverted by an inverter IV
4
, and a NMOS transistor N
8
controls the output of the data signal RDO depending on an input of the pipe counter signal PCNT. The first pull-up control unit
23
includes a PMOS transistor P
7
for outputting a pull-up signal depending on the output control signal DOFFZ applied from the first output control unit
12
of the driver driving control unit
10
.
The first pull-down control unit
24
includes a NMOS transistor P
9
for outputting a pull-down signal depending on the output control signal DOFF applied from the first output control unit
12
of the driver driving control unit
10
. The first output driver
25
includes a PMOS transistor P
8
and a NMOS transistor N
10
. The PMOS transistor P
8
outputs the output data to a data output pin DQ depending on a pull-up signal UPZ applied from the pull-up control unit
20
. Also, the NMOS transistor N
10
outputs the output data to a data output pin DQ depending on a pull-down signal DN applied from the pull-down control unit
24
.
An operation of the conventional data output buffer with this construction will be described with reference to the timing diagram of FIG.
2
.
First, if a read command READ is inputted, the output enable signal OE becomes HIGH and the output of the first level shifter
12
becomes HIGH, so that the output control signal DOFFZ is inputted to the first output control unit
12
. The first output control unit
12
inverts the output control signal DOFFZ using the inverter IV
2
to produce the output control signal DOFF with a LOW level. The data signal RDO applied from the memory cell is applied to the data output terminal of the data output driver
20
.
Next, during a NOP period where the read command READ is not applied, the output control signal DOFF becomes HIGH. The output of the first output driver
25
then moves to a HIGH impedance state.
Thereafter, when the semiconductor device is not driven, such as if a deep power down mode is set in order to reduce the power consumption, all internal supply voltages within the semiconductor memory device are not supplied. At this time, the levels of the output control signal DOFF and the output control signal DOFFZ, which control the output of the data output driver
20
, become unstable. Therefore, the pull-up signal UPZ and the pull-down signal DN of the first pull-up control unit
23
and the first pull-down control unit
24
, respectively, cannot maintain a stable level state.
In the case where an external power is used in the data output driver
20
, and the pull-up signal UPZ becomes LOW, the output data becomes HIGH since the PMOS transistor P
8
of the first output driver
25
is turned on (Case 1). Also, if the pull-down signal DN becomes HIGH, the output data becomes LOW since the NMOS transistor N
10
of the first output driver
25
is turned on (Case 2). Further, if the pull-up signal UPZ is LOW and the pull-down signal DN is HIGH, since the PMOS transistor P
8
and the NMOS transistor N
10
are turned on (Case 3), a current path is formed at the output terminal of the output driver
25
.
On the contrary, in the case where an internal power voltage is used in the data output driver
20
, a current path is formed through the data bus line, the PMOS transistor P
8
and the NMOS transistor N
10
in the above mentioned Cases 1 and 2. Also, in the above Case 3, a current path is formed between the data bus line and the internal power voltage.
Upon initiation of a deep power down mode, it is required that the output data be kept to be a HIGH impedance. However, due to formation of the current path, the output data does not keep HIGH impedance and the output data is transmitted to the output terminal. As a result, current is consumed in the data bus line.
SUMMARY OF THE DISCLOSURE
The present disclosed apparatus reduces unnecessary power consumption by preventing a current path, thereby improving an output control unit for controlling a data output driver upon a deep power down mode to maintain a HIGH impedance.
A data output buffer is disclosed including a driver driving control unit configured to control an output of data depending on the a state of an output enable signal. The data output buffer also includes a data output driver configured to transmit the data to a data output terminal according to the driving control unit. The driver driving control unit also includes a level shifter for shifting the level of an input voltage depending on the output enable signal. The driver driving control unit also includes an output control unit for controlling the output of the data output driver to be placed in a high impedance state depending on the state of an output signal of the level shifter and a deep power down signal that is enabled upon initiation of a deep power down mode.
Further disclosed is a data output buffer comprising a driver driving control unit configured to output an output control signal to control an output of data depending on a state of an output enable signal. Further included is a data output driv

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