Data normalization technique

Details Data normalization technique Data normalization technique

2000-07-06

2004-03-16

Tung, Kee M. (Department: 2671)

Computer graphics processing and selective visual display system

Computer graphics processing

Graphic manipulation

C345S501000

Reexamination Certificate

active

06707463

ABSTRACT:

MICROFICHE APPENDIX
There are 2 microfiche in total, and 103 frames in total.
FIELD OF THE INVENTION
The present invention relates to the field of creation of graphical images on a computer device such as a computer graphics coprocessor unit connected to an overall computer system, the graphics coprocessor assisting in the creation of images.
BACKGROUND OF THE INVENTION
Computer graphical images tend to come in many different forms. For example, in the past, only black and white bitmap displays were available and hence bitmaps having one bit per pixel were utilised. Subsequently, colored displays have become more significant and, as a result, a format comprising 8 bits per color channel of red, green and blue pixel data has become significant.
Over time, a technique of combining multiple images, each image having a transparency component, has become popular, resulting in a further opacity channel being added to pixel data. Further, output color display devices often utilise different color space mapping techniques, and hence other forms of color space representations (YUV or CYMK, for example) are also popular.
As a result of these and other developments, graphical objects utilized in the creation of computer graphic images may be presented in any of a large number of formats, making it relatively difficult for a processor or co-processor to deal with arbitrary graphical objects at relatively high speeds.
It is an object of the present invention to overcome or at least ameliorate one or more of the disadvantages of the prior art.
SUMMARY OF THE INVENTION
Accordingly, the invention provides a graphics processor for performing graphical operations on graphical objects, each of the graphical objects being represented in an external data format selected from a set thereof , the graphics processor including:
first mapping means to map each of the external data formats to a corresponding internal data format selected from a set of internal data formats;
calculation means to perform graphical operations on the graphical objects when in the
second mapping means to map each of the data formats in the set of internal data formats to a data format selected from the set of external data formats after the graphical operations have been performed.
Preferably, the set of external data formats include a contiguous stream of data of up to four channels per data quantum. Preferably also, each channel consists of 1-, 2-, 4-, 8-, or 16-bit samples.
Desirably, the external data format set includes an unpacked bit stream format consisting of a sequence of words, each word containing a predetermined number of valid bits.
In one preferred form, the internal data format set includes a 32-bit word format, each 32-bit word comprising four active-byte channels. Preferably, the internal data format set also includes an unpacked byte, 32-bit word format, each 32-bit word containing one active-byte channel.
A a particularly preferred embodiment, the first and second mapping means are each configured to perform one or more of at least the following mapping operations:
byte substitution;
byte lane-swapping; and
data replication.
In the following detailed description, the reader's attention is directed, in particular, to FIG.
2
and any one or more of
FIGS. 22
to
48
, and their associated description, without intending to detract from the disclosure of the remainder of the description.
TABLE OF CONTENTS
1.0 Brief Description of the Drawings
2.0 List of Tables
3.0 Description of the Preferred and Other Embodiments
3.1 General Arrangement of Plural Stream Architecture
3.2 Host/Co-processor Queuing
3.3 Register Description of Co-processor
3.4 Format of Plural Streams
3.5 Determine Current Active Stream
3.6 Fetch Instruction of Current Active Stream
3.7 Decode and Execute Instruction
3.8 Update Registers of Instruction Controller
3.9 Semantics of the Register Access Semaphore
3.10 Instruction Controller
3.11 Description of a Modules Local Register File
3.12 Register Read/Write Handling
13.13 Memory Area Read/Write Handling
3.14 CBus Structure
3.15 Co-processor Data Types and Data Manipulation
3.16 Data Normalization Circuit
3.17 Image Processing Operations of Accelator Card
3.17.1 Compositing
3.17.2 Color Space Conversion Instructions
a. Single Output General Color Space (SOGCS) Conversion Mode
b. Multiple Output General Color Space Mode
3.17.3 JPEG Coding/Decoding
a. Encoding
b. Decoding
3.17.4 Table Indexing
3.17.5 Data Coding Instructions
3.17.6 A Fast DCT Apparatus
3.17.7 Huffman Decoder
3.17.8 Image Transformation Instructions
3.17.9 Convolution Instructions
3.17.10 Matrix Multiplication
3.17.11 Halftoning
3.17.12 Hierarchial Image Format Decompression
3.17.13 Memory Copy Instructions
a. General purpose data movement instructions
b. Local DMA instructions
3.17.14 Flow Control Instructions
3.18 Modules of the Accelerator Card
3.18.1 Pixel Organizer
3.18.2 MUV Buffer
3.18.3 Result Organizer
3.18.4 Operand Organizers B and C
3.18.5 Main Data Path Unit
3.18.6 Data Cache Controller and Cache
a. Normal Cache Mode
b. The Single Output General Color Space Conversion Mode
c. Multiple Output General Color Space Conversion Mode
d. JPEG Encoding Mode
e. Slow JPEG Decoding Mode
f. Matrix Multiplication Mode
g. Disabled Mode
h. Invalidate Mode
3.18.7 Input Interface Switch
3.18.8 Local Memory Controller
3.18.9 Miscellaneous Module
3.18.10 External Interface Controller
3.18.11 Peripheral Interface Controller
APPENDIX A—Microprogramming
APPENDIX B—Register tables


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