Multiplex communications – Wide area network – Packet switching
Patent
1987-01-21
1988-12-27
Griffin, Robert L.
Multiplex communications
Wide area network
Packet switching
370103, H04J 304
Patent
active
047945966
DESCRIPTION:
BRIEF SUMMARY
This invention relates to a synchronised data network, and to a device for maintaining the synchronisation of the data network in the event of failure of certain components of the network.
The successful transmission of data over data links is dependent on maintaining synchronised both ends of the link. The failure of clock sources or data lines may cause the network to "free run", or one site may be timed by a clock source unsynchronised with respect to the clock source at another site.
It is the object of the present invention to provide a data network which will be maintained in synchronisation even in the event of failure of some of the components of the network.
Accordingly, there is provided a data network comprising a plurality of multiplexers connected one to another by data links; a plurality of clock sources; and a plurality of clock selectors, each clock selector being associate with one of the multiplexers, wherein there is provided means for generating one or more test signals, the clock selectors being adapted to receive one or more of the test signals, determine the presence or otherwise of the test signals to establish the status of one or more incoming clock signals, select one clock signal in predetermined hierarchical order and supply said clock signal to its associated multiplexer, or alternatively set its associated multiplexer to Slave to Receive mode in which the associated multiplexer takes incoming clock signals from one of the other multiplexers as its timing source.
The test signals may be received either directly from a clock source, or from a remote multiplexer to establish the status of the intervening data link. In some cases, therefore, the test will be on the condition of the data network, rather than a direct test on an incoming clock signal. The one or more clock selectors are conveniently adapted to set their associated multiplexers to Slave to Receive mode in the absence of all of the one or more test signals.
Preferably at least one clock selector is provided with one or more auxilary clock sources, the at least one clokk selector being adapted to supply clock signals from one of the one or more auxilary clock sources to its associated multiplexer in the absence of incoming clock signals from all of the other multiplexers.
Conveniently the clock sources are synchronised one to another. This allows remote multiplexers to be synchronised from their own local synchronised clock source, as opposed to from a single master clock.
The invention further resides in a data network comprising a plurality of multiplexers connected one to another by data links; a plurality of clock sources; means for generating one or more test signals; and a plurality of clock selectors, each clock selector being associated with one of the multiplexers, and comprising clock input means by which one or more clock signals are input to the clock selector, test input means by which one or more test signals are input to the clock selector, a test unit for determining the presence or otherwise of the one or more test signals, and switch means for selecting one clock signal in predetermined hierarchical order and supplying the said clock signal to its associated multiplexer, or alternatively setting its associated multiplexer to Slave to Receive mode in which the associated multiplexer takes incoming clock signals from on of the other multiplexers as its timing source, the switch means being actuated by signals from the test unit.
The means for generating one or more test signals preferably comprises one or more of the multiplexers. In this way, failure of a remote multiplexer or the intervening data link will cause an absence of a tsst signal, initiating action by one or more of the clock selectors.
The invention further resides in a clock selector adapted to be associated with a multiplexer and having clock input means by which one or more clock signals are input to the clock selector; test input means by which one or more test signals are input to the clock selector; a test unit for determining the pr
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Gloyne Francis R.
Harvey Philip D.
Chin Stephen
Griffin Robert L.
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