Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-10-12
2001-08-07
Malzahn, David H. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C712S221000
Reexamination Certificate
active
06272512
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of computer systems, and specifically, to a data manipulation instruction for enhancing value and efficiency of performing complex arithmetic instructions.
2. Background Information
To improve the efficiency of multimedia applications, as well as other applications with similar characteristics, a Single Instruction, Multiple Data (SIMD) architecture has been implemented in computer systems to enable one instruction to operate on several operands simultaneously, rather than on a single operand. In particular, SIMD architectures take advantage of packing many data elements within one register or memory location. With parallel hardware execution, multiple operations can be performed on separate data elements with one instruction, resulting in a significant performance improvement. The SIMD architecture applies to both integer and floating-point operands.
The SIMD data format of packing data elements within a register or memory location is a natural format for representing complex data. That is, first and second data elements of an operand may comprise real and imaginary components of the complex number, respectively. Many applications require the multiplication of complex numbers such as, for example, signal processing applications. To increase the efficiency of these applications, it is therefore desirable to reduce the number of instructions required for performing a complex multiply.
SUMMARY OF THE INVENTION
The present invention comprises a method and apparatus for performing complex arithmetic. In one embodiment, a method comprises decoding a single instruction, and in response to decoding the single instruction, moving a first operand occupying lower order bits of a first storage area to higher order bits of a result, moving a second operand occupying higher order bits of a second storage area to lower order bits of the result, and negating one of the first and second operands of the result.
REFERENCES:
patent: 5473557 (1995-12-01), Harrison et al.
patent: 5859997 (1999-01-01), Peleg et al.
patent: 5936872 (1999-08-01), Fischer et al.
patent: 5953241 (1999-09-01), Hansen et al.
Dulong Carole
Golliver Roger A.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Malzahn David H.
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