Data line management in a memory device

Details Data line management in a memory device Data line management in a memory device

2011-07-12

2011-07-12

Pham, Ly D (Department: 2827)

Static information storage and retrieval

Floating gate

Disturbance control

C365S185170, C365S185180, C365S185230, C365S185280

Reexamination Certificate

active

07978511

ABSTRACT:
Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods are provided. According to at least one such method, multiple pages of memory cells are inhibited during a programming operation such that memory cells enabled for programming are separated by two or more inhibited memory cells of the same row of memory cells regardless of the intended pattern of data states to be programmed into that row of memory cells.

REFERENCES:
patent: 2006/0140011 (2006-06-01), Fong et al.
patent: 2008/0180998 (2008-07-01), Chen
patent: 2008/0219059 (2008-09-01), Li
patent: 2008/0259684 (2008-10-01), Shlick et al.
patent: 2009/0237999 (2009-09-01), Li
Chandrasekhar, “Memory Device Biasing Method and Apparatus”, U.S. Appl. No. 12/265,989 filed Nov. 6, 2008, 29 pgs.

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