Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-01-07
2001-07-31
Chow, Dennis-Doon (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S100000
Reexamination Certificate
active
06268841
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data line driver for a matrix display and to a matrix display including such a driver. The display may, for example, be of the thin film transistor (TFT) active matrix liquid crystal display (AMLCD) type and the driver may be integrated monolithically using silicon-on-insulator (SOI) technology.
DISCUSSION OF THE RELATED ART
FIG. 1
of the accompanying drawings illustrates a typical known type of active matrix display, for instance as disclosed by Lewis et al “Driver Circuits for AMLCDs”, Journal of the Society for Information Display, pages 56-64, 1995. The display comprises an active matrix
1
of N rows and M columns of picture elements (pixels). The M columns of pixels have data lines which are connected to a data line driver
2
whose input
3
receives serial image data to be displayed. The rows of pixels are connected to scan lines which are connected to a scan line driver
4
. The scan line driver
4
supplies scanning or strobe signals for controlling the refreshing of the pixels with the image data.
The lower part of
FIG. 1
illustrates to an enlarged scale part of the active matrix
1
showing the individual pixels. Each pixel has a pixel electrode
5
controlled by a thin film transistor
6
. Each transistor
6
has a gate connected to the common row scan line such as
7
and a source connected to a common column data line such as
8
. The drain of the transistor
6
is connected to the electrode
5
.
In order to refresh the image data displayed by each pixel, the appropriate voltage is applied to the data line
8
so as to be present at the source of the pixel transistor
6
. The scan line driver
4
supplies a strobe pulse with the appropriate timing via the scan line
7
to the gate of the transistor
6
so that the transistor is switched from its non-conducting state to its conducting state. The charge from the data line is thus transferred to the pixel storage capacitance until the voltage on the electrode
5
is substantially equal to the voltage supplied by the data line driver
2
to the corresponding data line. When refreshing of the pixel has been completed, the strobe signal is removed by the driver
4
so that the transistor
6
returns to its non-conducting state until a further refresh cycle for the pixel takes place.
A display of the type shown in
FIG. 1
may be used with a point-at-a-time driving scheme, for instance in the case of an analogue display of small size and low pixel resolution. In this case, the driver
2
comprises a respective pair of complimentary sampling transistors forming a transmission gate connected between each data line
8
and the input
3
. A shift register controls conduction of the transmission gates such that only one gate at a time is conducting. An analogue video signal representing one row or line of image data to be displayed is supplied to the input
3
and the corresponding row of the matrix
1
is enabled by the scan line driver
4
applying a strobe signal to the corresponding scan line
7
. Each of the transmission gates of the data line driver
2
is enabled in turn by the shift register of the driver
2
in synchronism with the image data so that the pixels of the enabled line or row are refreshed one at a time in sequence.
When the line of pixels has been refreshed, the scan line driver
4
enables the next row of pixels and the process is repeated until all of the lines of pixels have been refreshed. The process is then repeated for each frame of image data supplied in sequence to the display.
For a display having a frame refresh rate f and comprising a matrix of N by M pixels, the data rate frequency of the image data, for each colour in the case of a colour display, is fNM. Thus, the time available for refreshing each pixel is less than or equal to 1/fNM. The combined resistances of each transmission gate, each data line
8
, and each pixel transistor
6
when conducting may amount to several kilohms and, together with the parasitic capacitance of the data line, the pixel storage capacitance and the liquid crystal capacitance, which may amount to several tens of picofarads, forms a time constant which must be sufficiently smaller than the pixel refresh period in order for the display to be properly refreshed. This places constraints on the size of the display and the frame refresh rate which can be achieved. Although it is possible to use multi-phase signals to perform concurrent point-at-a-time driving, the signal processing required to generate the required multi-phase display data signals is substantial.
For large displays where multi-phase point-at-a-time driving is unfeasible, line-at-a-time driving is used to allow substantially more time for data line charging. This technique may be used with analogue image data or with digital image data by providing digital-to-analogue conversion within the data line driver
2
.
FIG. 2
of the accompanying drawings illustrates a display providing line-at-a-time driving with digital image data. The display comprises an active matrix
1
of pixels, for instance of the type shown in FIG.
1
. The data line driver
2
of
FIG. 1
is replaced by “top” and “bottom” digital data drivers
2
a
and
2
b
physically disposed above and below the active matrix
1
. This is often necessary because of the large area required for the driver electronics. The drivers
2
a
and
2
b
drive respective sets of interleaved data lines
8
a
and
8
b
. The scan line driver
4
is of the same type as shown in FIG.
1
and supplies scan or strobe signals S
1
, . . . SN one at a time in a repeating sequence to the scan lines
7
.
Each of the data drivers
2
a
,
2
b
comprises control logic
9
a
,
9
b
which receives control and synchronisation signals FPVDCK (flat panel video clock), FPDE (flat panel display enable) and HSYNC (horiztonal synchronisation) and which supplies the appropriate control signals to the remainder of the driver. Each of the drivers
2
a
and
2
b
comprises an input register
10
a
,
10
b
, a storage register
11
a
,
11
b
and a digital-to-analogue (D/A) converter array
12
a
,
12
b
. Each input register is connected to a colour data input bus receiving n digit image data for red, green and blue image pixels. Each converter array
12
a
and
12
b
receives gamma correction reference voltages which are used in D/A conversion to compensate for the liquid crystal voltage—transmission non-linearity. The scan line driver
4
receives the signals HSYNC and VSYNC (horizontal and vertical synchronising signals).
Red, green and blue image data, indicated by R (0:n−1), G(0:n−1) and B(0:n−1) in
FIG. 2
, are supplied as n bit parallel data with the data for the pixels being supplied sequentially. The input register
10
a
,
10
b
comprises a series shift register having a plurality of stages, each of which comprises a 3n bit register. The stages of the register
10
a
,
10
b
have parallel outputs connected to the storage register
11
a
,
11
b
, which comprises a number of 3n bit latches equal to the number of shift register stages.
The digital image data are entered a line at a time in the input register
10
a
. When a full line of data has been entered, the data are transferred from the input register
10
a
,
10
b
to the storage register
11
a
,
11
b
. A scan signal is applied to the scan line
7
of the row of pixels to be refreshed. The converter array
12
a
,
12
b
converts the image stored in the latches of the register
11
a
,
11
b
into the appropriate data voltages and supplies these to the data lines
8
a
,
8
b
. Thus, a complete line or row of pixels is updated at a time.
During updating of a row of pixels, image data for the next row of pixels are entered in the input shift register
10
a
,
10
b
. When the input register has received the complete row of image data, the image data are transferred to the storage register and the scan line driver
4
supplies a signal to the scan line
7
of the next row of pixels to be updated.
Using this technique, the pixels of each
Brownlow Michael James
Cairns Graham Andrew
Kay Andrew
Chow Dennis-Doon
Renner Otto Boisselle & Sklar
Sharp Kabushiki Kaisha
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