Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
1998-11-25
2001-06-19
Shalwala, Bipin (Department: 2778)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S204000, C315S169100
Reexamination Certificate
active
06249279
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a matrix display panel such as a plasma display, liquid crystal panel, electroluminescent panel and the like, and in particular to a data line drive device for driving the matrix of the display panel.
RELATED ART
Typical matrix display panel include plasma display, liquid crystal panel, electroluminescent panel and the like. The present invention will be described with reference to a plasma display panel. Referring now to
FIG. 7
, there are shown only the lines of the plasma display panel. PDP denotes a plasma display panel. First and second insulating substrates
11
and
12
which will be described hereafter are sandwiched at a seal portion along the periphery of the panel so that a space therebetween is filled with a discharge gas. S
1
, S
2
, . . . , Sm denote scanning lines. Ca
1
, Ca
2
, Cam denote hold lines. Da
1
, Da
2
, Dam-
1
, Dan denote data lines. SDR denotes a circuit driving the scanning lines. CDR denotes a circuit driving the hold lines. DDR denotes a circuit driving the data lines. A display cell CELL at an intersection between ith scanning line and jth data line is represented by aij.
The section of the plasma display panel PDP is shown in FIG.
8
.
FIG. 8
is a sectional view taken along the data line in FIG.
7
. In
FIG. 8
, a reference numeral
11
denotes the first insulating substrate made of glass;
12
the second insulating substrate also made of glass;
13
a data line of a metallic electrode;
14
an insulating layer covering the data line
13
;
15
a barrier made of an insulating material such as glass;
16
a fluorescent material;
17
a scanning line including a transparent electrode such as NESA electrode;
18
a hold line including a transparent electrode such as NESA electrode;
19
a bus line made of a metal used for lowering the resistance of the scanning line
17
and the hold line
18
;
20
a thick insulating layer;
21
a barrier made of an insulating material;
22
a protective layer made of MgO and the like for protecting the insulating layer from gas discharge; and
23
a discharge gas space which is filled with a discharge gas such as rare gas for exiting the fluorescent material with electric discharge. Preferable display direction of image is shown by an arrow in FIG.
8
.
Referring now to
FIG. 9
, there is shown an example of the drive voltage waveform and light emission waveform of the plasma display panel which is shown in
FIGS. 7 and 8
. Waveform (A) denotes the waveform of the voltage which is applied to the hold lines Ca
1
, Ca
2
, Cam. Waveform (B) denotes the waveform of the voltage which is applied to the scanning line S
1
. Waveform (C) denotes the waveform of the voltage applied to the scanning line S
2
. Waveform (D) denotes the waveform of the voltage applied to the scanning line Sm. Waveform (E) and (F) denote the waveforms of the voltages which are applied to the data lines Da
1
and Da
2
, respectively. Waveform (G) denotes the waveform of the light emission from a display cell a
11
. The hatching of pluses in the waveforms (E) and (F) shows that presence or absence of the pulse is determined in accordance with the presence or absence of data to be written.
Now, operation is described. Firstly, electric discharge which has been sustained is eliminated with an eliminating pulse P
1
. Then, a priming pulse P
2
is applied to all the hold lines
18
so that priming discharge occurs over the entire area of the panel, generating priming particles which will become seeds for electric discharge on writing of the display data. Then, a priming eliminating pulse
37
is applied to all scanning lines while the priming discharge will not induce sustained discharge. Then, electric discharge for writing display data by applying a data pulse P
4
to the data line D
1
, D
2
, . . . , D
n−1
, D
n
in synchronization with the scanning pulse P
3
applied to the scanning lines S
1
, S
2
, . . . , Sm.
FIG. 9
shows that data is written into the display cells a
11
, a
22
, no data is written into the display cells a
12
, a
21
, display of the display cells other than the display cells a
11
, a
22
, a
12
, a
21
, at first and second rows and the display cells at third and following rows is achieved depending on presence and absence of the data. Sustained discharge is achieved between the scanning and hold lines
17
and
18
with the application of hold pulses P
5
and P
6
in the display cell
24
in which discharge for writing has been conducted. The display brightness is controlled by changing the number (frequency) of applications of the hold pulses P
5
and P
6
.
In the above-mentioned prior art driving method, however, power is required for charging or discharging electrostatic charges also on the scanning lines other than those which are not used for data writing each time when data on each scanning line is written in addition to power required for applying pulses on the data lines in the matrix display panel to drive the data line for writing data thereon. Besides, it is required to carry out charging and discharging of the electrostatic charge between neighboring data lines of the matrix display panel. Accordingly, the power consumption is high since power is required for writing data in addition to the power inherently necessary for displaying the matrix display panel. The problem becomes more significant as the matrix display panel becomes higher in display definition and larger in size.
Therefore, an electrostatic charge recovering circuit has been proposed which recovers the power used for discharging or charging the electrostatic charges of the panel with pulses in order to reduce the consumption of the power used for driving data lines of the matrix display panel as is described in, for example, Japanese Patent Kokai JP-A-Hei-8-16090(1996). This circuit is described with reference to FIG.
10
. In the drawing, a reference Z
100
denotes an integrated circuit for driving data lines of the matrix display panel; P
100
denotes a terminal for applying a d.c. voltage used for recovering electrostatic charges having a half of the data voltage Vd; P
101
a terminal for applying a d.c. voltage having a data voltage Vd; P
102
a terminal of the integrated circuit Z
100
for recovering the charges; P
103
a grounded terminal of the integrated circuit Z
100
; P
104
a terminal of the integrated circuit Z
100
for inputting a data voltage Vd.
References D
100
to D
102
denote diodes; C
100
a capacitor for recovering the charge stored in a resultant electrostatic capacitance of the data line, the electrostatic charge on which is to be recovered and an auxiliary capacitor; C
101
an auxiliary capacitor which reduces the rate of changes in the recovered electrostatic charge due to changes in the electrostatic capacitance of the data lines of the matrix display panel, the charge on which is to be recovered; L
100
denotes a coil for recovering the charge; Q
100
an N channel FET; Q
101
denotes a P channel FET; QA
100
to QA
10
N denote high breakdown voltage N channel transfer gates in the integrated circuit Z
100
; QN
100
to QN
10
N high breakdown voltage N channel FETs in the integrated circuit Z
100
; QP
100
to QP
10
N high breakdown voltage P channel FETs in the integrated circuit Z
100
; DN
100
to DN
10
N denote parasitic diodes of the N channel FETs (QN
100
to QN
10
N); DP
100
to DP
10
N parasitic diodes of the P channel FETs (QP
100
to QP
10
N).
References PZ
100
to PZ
10
N denote output terminals of the integrated circuit Z
100
, which are connected to the data lines of the matrix display panel;
100
A denotes a switch unit comprising the FETs Q
100
,
0101
and the diodes D
101
, D
102
;
100
B denotes a switch unit comprising the above-mentioned FETs QP
100
, QN
100
; the parasitic diodes DP
100
, DN
100
; and the transfer gates QA
100
(to QA
10
N); and
100
C denotes a data line of the matrix display panel.
The charge recovering circuit serves to recover the charge accumulated on each of the data lines of the matrix display panel to the charge rec
Lewis David L.
NEC Corporation
Shalwala Bipin
Sughrue Mion Zinn Macpeak & Seas, PLLC
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