Data line disturbance free memory block divided flash memory and

Details Data line disturbance free memory block divided flash memory and Data line disturbance free memory block divided flash memory and

1995-06-07

1998-06-16

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36523003, G11C 1134

Patent

active

057681945

ABSTRACT:
A single chip semiconductor integrated circuit device having a central processing unit (CPU) and a flash memory which stores data to be processed by the CPU and which provides data to the CPU through the data bus in response to accessing instructions from the CPU through the address bus. The flash memory is constituted by a plurality of memory arrays in which a plurality of word lines are commonly employed for all of the memory arrays and a plurality of data lines are distributed amongst the memory arrays. The nonvolatile memory cells are arranged in a manner in which plural memory blocks are formed. The memory blocks formed can be facilitated with different memory capacities. This is achieved by having one or more rows of memory cells associated with one or more word lines provided within a memory block. Sources of all of the memory cells within each memory block are connected to a single source line which is fed by a predetermined voltage for effecting simultaneous erasure of the memory cells therein from a corresponding one of plural source voltage control circuits. In accordance with another feature of the flash memory, individual ones of plural bit data are assigned to respective ones of the plural memory arrays.

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