Data line disturbance free memory block divided flash memory and

Details Data line disturbance free memory block divided flash memory and Data line disturbance free memory block divided flash memory and

1995-07-31

1996-12-03

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

365218, 36518511, 36518514, G11C 1134

Patent

active

055815030

ABSTRACT:
An electrically rewritable flash memory device which has a memory cell array arranged in rows and columns of memory cells and which is divided into a plurality of memory blocks having different memory capacities. Each memory block having one or more rows of memory cells. A common voltage control circuit is provided for each of the memory blocks for applying a first potential to a common conductor for a memory block containing a memory cell selected with a selection voltage applied to its associated data line conductor for a writing operation and a second potential higher than the first potential to a common conductor for a memory block containing a memory cell unselected with the selection voltage applied to its associated data line conductor and containing no selected memory cell for a writing operation. A microcomputer having a CPU and the above-mentioned electrically rewritable flash memory formed in a single semiconductor chip includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of the CPU and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

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