Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-02-27
2002-07-02
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185110
Reexamination Certificate
active
06414878
ABSTRACT:
JP-A-2-289997 (Laid-open on Nov. 29, 1990) describes a simultaneous erasing type EEPROM. This simultaneous erasing type EEPROM can be described as operating as a flash memory, such as described in the present specification. In the flash memory, information can be rewritten by electrical erasing and writing, each memory cell can be constructed of a single transistor as in the EPROM and, functionally, all memory cells or a block of memory cells can be erased simultaneously by electrical erasing. Accordingly, in the flash memory, information stored therein can be rewritten with the flash memory mounted on a system, the time for rewrite can be shortened by virtue of its simultaneous erasing function and contribution to reduction of the area occupied by a chip can be accomplished.
U.S. Pat. No. 5,065,364 (issued on Nov. 12, 1991) shows a flash memory of the type in which an array of electrically erasable and rewritable memory cells having control gates, drains and sources is divided into a plurality of memory blocks in a unit of data line, source lines in common to each block are led out and a voltage complying with an operation is applied separately to a source line by means of a source switch provided in each source line. At that time, ground potential is applied to the source line of a block selected for writing. A voltage VDI of, for example, 3.5V is applied to the source line of a block not selected for writing. The voltage VDI guards against word line disturbance. The word line disturbance referred to herein is a phenomenon that for example, in a memory cell having a word line conditioned for selection and a data line conditioned for unselection, the potential difference between the control gate and floating gate is increased and as a result, electric charge is discharged from floating gate to control gate to decrease the threshold of the memory cell transistor.
JP-A-59-29488 (laid-open on Feb. 16, 1991) and JP-A-3-78195 (laid-open on Apr. 3, 1991) describe an ultraviolet light-erasable EPROM in which sources of memory cells connected with the same word line are connected in common and a source potential control switch is provided for the commonly connected sources. JP-A-3-78195 (laid-open on Apr. 3, 1991) describes an ultraviolet light-erasable EPROM in which sources of memory cells connected with adjacent two word lines are connected in common and a source potential control switch is provided for each adjacent two word lines. Each of the inventions disclosed in these three references is intended to provide a solution to a problem of erroneous writing/reading caused by leak current from an unselected memory cell in an EEPROM.
U.S. application Ser. No. 07/942,028 filed Sep. 8, 1992, which is a continuation application of U.S. application Ser. No. 07/568,071 filed Aug. 16, 1990, discloses a structure of a flash memory in which sources of memory cells are connected in common for the purpose of preventing a word line disturb problem for a writing operation.
Meanwhile, JP-A-3-14272 (laid-open on Jan. 22, 1991), JP-A-3-250495 (laid-open on Nov. 8, 1991) and JP-A-2-241060 (laid-open on Sep. 25, 1990) describe division of a memory cell array in a unit to data line.
SUMMARY OF THE INVENTION
The present inventors have first studied the fact that a flash memory is carried on a microcomputer to find out the following points.
(1) Programs and data are stored in a ROM incorporated or built in the microcomputer. Data is classified into data of a large capacity and data of a small capacity. When the programs and data are to be rewritten, the former data is typically rewritten in a large unit of severals of tens of KB (kilobyte) and the latter data is typically rewritten in a small unit of severals of tens of B (byte). At that time, if the flash memory is erased in a unit of chip batch or in a unit of memory block of the same size, inconvenience that the erase unit matches with a program area but is excessively large for a data area to impair ease of use thereof may occur or the converse case may occur.
(2) When part of information held in the flash memory is desired to be rewritten after the microcomputer is mounted on a system, it suffices to use part of the memory block holding the information of interest as an object to be rewritten. But if all simultaneously erasable memory blocks have an equal storage capacity, then even when rewrite of only a smaller amount of information than the storage capacity of a memory block is desired, the memory block of a relatively large storage capacity must be erased simultaneously and thereafter write is carried out over the whole of the memory block in question, with the result that time is consumed wastefully for rewrite of information not substantially required to be rewritten.
(3) Information to be written into the flash memory is determined in accordance with the system to which the microcomputer is applied but efficiency may sometimes be degraded when the information is all written from the beginning with the microcomputer of interest mounted on the system.
(4) When the flash memory is rewritten with the microcomputer mounted, it sometimes suffices that only part of information of a memory block, standing for an object to be rewritten, is rewritten. But even in this case, if information to be written into the whole of the memory block which has been erased simultaneously is all received sequentially externally of the microcomputer and rewritten, all of the information to be written into the whole of the memory block of interest will have to be received from the outside in spite of the fact that it suffices to rewrite only part of information of the memory block to be rewritten, and transfer, from the outside, of information not substantially required to be rewritten, that is, information held internally in advance of rewrite must be repeated, resulting in wastefulness of transfer of information for partial rewrite of the memory block.
(5) Because of information storing mechanism, the time for rewriting the flash memory through simultaneous erasing is far longer as compared to a memory such as RAM (random access memory) and so the flash memory cannot be rewritten on real time base in synchronism with machine control operation by the microcomputer.
The present inventors have studied the division of memory blocks in a unit of data line to find that the size of the minimum memory block can be decreased more easily by division into memory blocks in a unit of word line and using sources in common in a block and this is advantageous also from the standpoint of improving ease of use of the flash memory built in the microcomputer as studied firstly. When the division into memory blocks in a unit of data line is employed, all memory cells of a selected block for writing arranged in line and having drains connected to a data line applied with a write high voltage suffer from data line disturbance. The data line disturbance is a phenomenon that for example, in a memory cell associated with a word line not rendered to be selected and a data line rendered to be selected for writing, an electric field between the source and drain is increased, so that hot holes are injected from drain to floating gate to decrease the threshold of the memory cell transistor.
A major object of the invention is to provide a microcomputer incorporating a flash memory which is easy to use. More particularly, a first object of the invention is to provide a microcomputer capable of making highly efficient a processing of initial write of information into the built-in flash memory. A second object of the invention is to improve rewrite efficiency of part of information held in some of memory blocks of the flash memory by eliminating wastefulness of write operation after simultaneous erasing of the memory blocks of interest. A third object of the invention is to improve rewrite efficiency by eliminating wasteful transfer operation, from the outside, of write information necessary for partial rewrite of a memory block. A fourth object of the invention is to change information held in the
Baba Shiro
Ito Takashi
Kuroda Kenichi
Matsubara Kiyoshi
Mukai Hirofumi
Hitachi , Ltd.
Ho Hoai V.
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