Data-level clock recovery

Details Data-level clock recovery Data-level clock recovery

2006-07-05

2008-08-12

Bayard, Emmanuel (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S355000, C375S360000

Reexamination Certificate

active

07412016

ABSTRACT:
A circuit for adjusting the phase of a clock signal. A first sampling circuit generates a sequence of data samples in response to transitions of the clock signal, each of the data samples having either a first state or a second state according to whether an incoming signal exceeds a first threshold. An second sampling circuit generates an error sample in response to one of the transitions of the clock signal, the error sample having either the first state or the second state according to whether the incoming signal exceeds a second threshold. A phase adjust circuit adjusts the phase of the clock signal if the sequence of data samples matches a predetermined pattern and based, at least in part, on whether the error sample has the first state or the second state.

REFERENCES:
patent: 3534273 (1970-10-01), Thomas
patent: 3582879 (1971-06-01), Sullivan
patent: 3775688 (1973-11-01), Hinoshita et al.
patent: 3992616 (1976-11-01), Acker
patent: 4584559 (1986-04-01), Penney
patent: 4615038 (1986-09-01), Lim, deceased et al.
patent: 4709376 (1987-11-01), Kage
patent: 4719396 (1988-01-01), Asano et al.
patent: 4730343 (1988-03-01), Kanemasa et al.
patent: 4970609 (1990-11-01), Cunningham et al.
patent: 4992677 (1991-02-01), Ishibashi et al.
patent: 5014226 (1991-05-01), Horstmann
patent: 5036525 (1991-07-01), Wong
patent: 5122690 (1992-06-01), Bianchi
patent: 5191462 (1993-03-01), Gitlin et al.
patent: 5194462 (1993-03-01), Gitlin et al.
patent: 5268930 (1993-12-01), Sendyk et al.
patent: 5402378 (1995-03-01), Min et al.
patent: 5402445 (1995-03-01), Matsuura
patent: 5425033 (1995-06-01), Jessop et al.
patent: 5448200 (1995-09-01), Fernandez et al.
patent: 5455844 (1995-10-01), Ishikawa et al.
patent: 5459762 (1995-10-01), Wang et al.
patent: 5465093 (1995-11-01), Kusumoto et al.
patent: 5490169 (1996-02-01), Blackwell et al.
patent: 5546424 (1996-08-01), Miyake
patent: 5596285 (1997-01-01), Marbot
patent: 5659581 (1997-08-01), Betts et al.
patent: 5668830 (1997-09-01), Georgiou et al.
patent: 5675588 (1997-10-01), Maruyama
patent: 5742798 (1998-04-01), Goldrian
patent: 5757297 (1998-05-01), Ferraiolo et al.
patent: 5757857 (1998-05-01), Buchwald
patent: 5778217 (1998-07-01), Kao
patent: 5802105 (1998-09-01), Tiedemann, Jr. et al.
patent: 5875177 (1999-02-01), Uriu et al.
patent: 5877647 (1999-03-01), Vajapey
patent: 5896067 (1999-04-01), Williams
patent: 5898321 (1999-04-01), Ilkbahar
patent: 5940442 (1999-08-01), Wong
patent: 6108801 (2000-08-01), Malhotra et al.
patent: 6118824 (2000-09-01), Smith et al.
patent: 6122757 (2000-09-01), Kelley
patent: 6262591 (2001-07-01), Hui
patent: 6288563 (2001-09-01), Muljono
patent: 6304071 (2001-10-01), Popplewell et al.
patent: 6380758 (2002-04-01), Hsu
patent: 6417100 (2002-07-01), Hirata et al.
patent: 6448806 (2002-09-01), Roth
patent: 6509756 (2003-01-01), Yu
patent: 6541966 (2003-04-01), Keene
patent: 6541996 (2003-04-01), Rosefield et al.
patent: 6574758 (2003-06-01), Eccles
patent: 6628621 (2003-09-01), Appleton
patent: 6707325 (2004-03-01), Taguchi
patent: 6717985 (2004-04-01), Poon
patent: 6724329 (2004-04-01), Casper
patent: 6760389 (2004-07-01), Mukherjee
patent: 6760574 (2004-07-01), Lu et al.
patent: 6839861 (2005-01-01), Hoke et al.
patent: 6885691 (2005-04-01), Lyu
patent: 6897712 (2005-05-01), Ficken
patent: 6941483 (2005-09-01), Brown
patent: 6970681 (2005-11-01), Darabi et al.
patent: 6979987 (2005-12-01), Kernahan et al.
patent: 7016445 (2006-03-01), Bronfer et al.
patent: 7054402 (2006-05-01), Muellner
patent: 7092472 (2006-08-01), Stojanovic
patent: 7099400 (2006-08-01), Yang et al.
patent: 2001/0043649 (2001-11-01), Farjad-Rad
patent: 2002/0150184 (2002-10-01), Hafeez et al.
patent: 2003/0002602 (2003-01-01), Kwon et al.
patent: 2003/0016091 (2003-01-01), Casper
patent: 2003/0063664 (2003-04-01), Bodenschatz
patent: 2003/0070126 (2003-04-01), Werner
patent: 2003/0084385 (2003-05-01), Zerbe et al.
patent: 2003/0093713 (2003-05-01), Werner
patent: 2003/0108096 (2003-06-01), Steinbach
patent: 2003/0159094 (2003-08-01), Smith et al.
patent: 2003/0208707 (2003-11-01), Zerbe
patent: 2004/0001567 (2004-01-01), Wei
patent: 2004/0022311 (2004-02-01), Zerbe et al.
patent: 2004/0071203 (2004-04-01), Gorecki
patent: 2004/0071204 (2004-04-01), Gorecki
patent: 2004/0071205 (2004-04-01), Gorecki
patent: 2004/0076192 (2004-04-01), Zerbe
patent: 0365257 (1990-04-01), None
patent: 1331779 (2003-07-01), None
patent: 20035831 (2000-02-01), None
patent: 200035831 (2000-02-01), None
patent: WO00/011830 (2000-03-01), None
patent: WO03/025599 (2003-03-01), None
patent: WO03/032652 (2003-04-01), None
patent: WO04/008490 (2004-01-01), None
Aboulnasr, T. et al., “Characterization of a Symbol Rate Timing Recovery Technique for a 2B1Q Digital Receiver,” IEEE Trans. on Communications, vol. 42, Nos. 2/3/4, pp. 1409-1414, Feb.-Apr. 1994.
Armstrong, J. “Symbol Synchronization Using Baud-Rate Sampling and Data-Sequence-Dependent Signal Processing,” IEEE Trans. on Communications, vol. 39, No. 1, pp. 127-132, Jan. 1991.
Mueller, K. et al., “Timing Recovery in Digital Synchronous Data Receivers,” IEEE Trans. on Communications, vol. Com-24, No. 5, pp. 516-531, May 1976.
Hoke et al., Self-timed interface for S/390 I/O subsystem interconnection, International Business Machines Corporation, J. Res. Develop. vol. 43, No. 5/6, Sep./Nov. 1999.
Aaron Martin et al., “8Gb/s Differential Simultaneous Bidirectional Link with 4mV 9ps Waveform Capture Diagnostic Capability”, ISSCC 2003/Session 4/Clock Recovery and Backplane Transceivers/Paper 4.5, 2003 IEEE International Solid State Circuits Conference.
Cgen-Chu Yeh and John R. Barry, “Adaptive Minimum Bit-Error Rate Equalization for Binary Signaling,” IEEE Transactions on Communications, vol. 48, No. 7, Jul. 2000, pp. 1226-1235.
J.M. Hoke et al, self-timed Interface for S/390 I/O Subsystem Interconntion, IBM J.Res. Develop., vol. 43, No. 5/6, Sep./Nov. 1999, p. 829-846.
Jack H. Winters et al., “Adaptive Nonlinear Cancellation for High-Speed Fiber-Optic Systems”, Journal of Lightwave Technology, vol. 10, No. 7, Jul. 1992, IEEE, pp. 971-977.
Keshab K. Parhi, “High-Speed Architectures for Algorithms with Quantizer Loops”, IEEE, 1990, pp. 2357-2360.
Keshab K. Parhi, “Pipelining in Algorithms with Quantizer Loops”, IEEE Transactions on Circuits and Systems, vol. 38, No. 7, Jul. 1991, pp. 745-754.
Sanjay Kasturia et al., “Techniques for High-Speed Implementation on Nonlinear Cancellation”, IEEE Journal on Selected Areas in Communications, vol. 9, No. 5, Jun. 1991, pp. 711-717
Scott C. Douglas, “Fast Implementations of the Filtered-X LMS and LMS Algorithms for Multichannel Active Noise Control, ”IEEE Transactions on Speech and Audio Proc., vol. 7, No. 4, Jul. 1999, pp. 454-465.
Vladimir Stojanovic, George Ginis and Mark A. Horowitz, “Transmit Pre-emphasis for High-Speed Time-Division-Multiplexed Serial-Link Transceiver,” International Conference on Communications, New York, NY, May 2, 2002, pp. 1-6.

Affiliated with

Also associated with

Rating

Data-level clock recovery does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data-level clock recovery, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data-level clock recovery will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3997297