Data latch timing adjustment apparatus

Details Data latch timing adjustment apparatus Data latch timing adjustment apparatus

2005-06-28

2005-06-28

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S158000, C365S233100

Reexamination Certificate

active

06911851

ABSTRACT:
In a data latch timing adjustment apparatus, a read control section reads out a first checking data piece in a checking data storing section written in a memory and outputs a latch pulse signal to a delay selecting section. A selection part outputs, to a latch circuit, a delayed pulse signal obtained by delaying the latch pulse signal by the front delay circuit. The latch circuit delays the checking data piece from the memory at the reception of the delayed pulse signal. Then, the next data piece is read out from the memory and the selection part outputs, to the latch circuit, a delayed pulse signal delayed by the delay circuit at the preceding stage.

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patent: 5-342085 (1993-12-01), None
patent: P2001-350668 (2001-12-01), None

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