Data latch circuit of semiconductor device

Details Data latch circuit of semiconductor device Data latch circuit of semiconductor device

2007-09-04

2007-09-04

Cox, Cassandra (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C365S189050

Reexamination Certificate

active

11322765

ABSTRACT:
A data latch circuit for latching a data signal in synchronization with a clock signal includes a hold time delay unit for generating a first clock signal by delaying the clock signal for a hold time of the data signal and an inverse first clock signal as a second clock signal; a data input control unit for generating a first data transition detection signal in response to the first clock signal and a first transition timing of the data signal and a second data transition detection signal in response to the second clock signal and a second transition timing of the data signal; and a data latch unit for starting latching the data signal in response to the first data transition detection signal and finishing the latching of the data signal in response to the second data transition detection signal.

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