Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Fusible link or intentional destruct circuit
Reexamination Certificate
2003-06-16
2004-07-06
Nguyen, Long (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Fusible link or intentional destruct circuit
C327S526000, C327S524000, C365S225700, C326S037000
Reexamination Certificate
active
06759895
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a data latch circuit having anti-fuse elements and, more particularly, to a data latch circuit having functions of programming anti-fuse elements with desired data and delivering the nonvolatile data stored in the anti-fuse elements.
(b) Description of the Related Art
In an LSI including a memory circuit, it is difficult to perfectly exclude defects in some of the memory cells during manufacturing the memory circuit. To remedy a product memory device including therein one or more defective memory cells, redundant memory cells are generally used in the memory device to replace the detective memory cells by the redundant memory cells.
The remedy information as to the remedy of the defective memory cells by the redundant memory cells is stored in nonvolatile memory elements, such as EPROM elements which are electrically programmable, fuse elements which are fused by a critical current to assume an electrically open state, and anti-fuse elements (or non-fuse elements) which are applied with a critical voltage to be short-circuited due to the dielectric breakdown thereof.
Among other nonvolatile memory elements for storing the remedy information, the anti-fuse elements are generally preferable especially in a mixed LSI including together a logic macro block and a large-capacity memory macro block, such as SRAM and DRAM. The anti-fuse elements are superior to the EPROM elements which require a large number of fabrication steps and thus the increased costs thereof. The anti-fuse elements are superior to the fuse elements which prohibit metallic interconnections from being disposed overlying the fuse elements in view of the heat generated in the fuse elements during the fusing operation thereof and thus require an increased occupied area.
The anti-fuse elements have an advantage in that the current passing through the anti-fuse elements during the dielectric breakdown thereof is considerably smaller than the current used for fusing the fuse elements, especially in the case of capacitive anti-fuse elements, and thus the heat generated by the dielectric breakdown can be neglected for the safe operation.
However, there is a problem in the conventional anti-fuse elements that the anti-fuse elements have an average resistance around several hundreds of ohms after the dielectric breakdown, wherein some anti-fuse elements may have several tens of kilo-ohms at the maximum, although this is a relatively rare case. In the case of several tens of kilo-ohms for the resistance of the anti-fuse elements, the judgement whether the anti-fuse elements are conductive or non-conductive is difficult and must be performed by using a detector having a higher sensitivity.
JP domestic publication 2000-503794 for PCT describes a data latch circuit including a detector having an improved sensitivity for the data stored in the anti-fuse elements.
FIG. 11
shows the data latch circuit described in the publication, wherein anti-fuse elements to be detected for the resistances thereof are implemented as capacitive anti-fuse elements
77
and
78
.
A power supply voltage is applied through terminal VDD to the sources of pMOSFETs
71
and
72
, a programming voltage is applied through terminal VPRG to the sources of pMOSFETs
81
and
82
, first and second bypass voltages PB are applied to the gates of pMOSFETs
73
and
74
, respectively.
To program the capacitive anti-fuse elements
77
and
78
to a logic level “1”, capacitive anti-fuse element
77
is subjected to dielectric breakdown of the gate insulation film. More specifically, for the programming, nMOSFETs
75
,
76
,
79
,
80
and
84
are turned OFF, pMOSFET
81
and nMOSFET
83
v
are turned ON, and pMOSFET
82
is turned OFF. Due to the potential difference, which is equal to the programming voltage, between both the plates (electrodes) of capacitive element
77
, capacitive element
77
having a dielectric withstand voltage lower than the programming voltage is subjected to a dielectric breakdown, whereby the resistance of capacitive element
77
is reduced. On the other hand, since both the plates of capacitive element
78
have no potential difference therebetween, capacitive element
78
maintains a higher insulating resistance.
To read the data from the capacitive elements
77
and
78
in the data latch circuit, nMOSFETs
79
and
80
are turned ON, nMOSFETs
75
and
76
are applied with the bypass voltages PB, and pMOSFETs
81
and
82
and nMOSFETs
83
and
84
are turned OFF. The cross connection between the drain of each of pMOSFETs
71
and
72
and the gate of the other of pMOSFETs
71
and
72
allows a difference between the currents passing through the capacitive anti-fuse elements
77
and
78
to be amplified and delivered as an amplified difference signal from the detector. In this case, since the current passing through capacitive element
77
subjected to the dielectric breakdown is larger than the current passing through capacitive element
78
not subjected to dielectric breakdown, output terminal RCB assumes a low level whereas output terminal RC assumes a high level, thereby delivering a logic level “1” from the data latch circuit.
The conventional detector as described above can detect the stored data even from the capacitive anti-fuse element having a resistance as high as several tens of kilo-ohms after the dielectric breakdown. However, the above publication is silent to the concrete structure of the capacitive anti-fuse elements
77
and
78
except that the first-conductivity-type plate and second-conductivity-type plate are provided in the capacitive elements, and that the power supply voltage applied through terminals VDD is applied to these plates via nMOSFETs
75
and
76
effecting voltage drops.
It is considered from the description that each capacitive element has a thin dielectric film between the plates thereof, and that the thin dielectric film may be broken by direct application of the supply voltage. Since it is unclear whether or not the programming voltage is higher than the supply voltage, it is also unclear whether the pMOSFETs such as
81
and
82
applied with the programming voltage has a withstand voltage higher than the withstand voltage of pMOSFETs
71
and
72
applied with the supply voltage, or has a withstand voltage equal to the withstand voltage of pMOSFETs
71
and
72
.
In short, although the above publication describes the structure of the detector for detecting the data stored in the data latch circuit, the publication does not show the concrete structures of the anti-fuse elements and the transistor elements constituting the programming circuit and thus the concrete structure of the data latch circuit as a whole.
In addition, the detector described in the publication has a large occupied area because of a large number (
12
) of MOSFETs including eight high-withstand-voltage MOSFETs
81
,
82
,
75
,
76
,
79
,
80
,
83
and
84
including gates having a larger thickness, assuming that the programming voltage is higher than the supply voltage.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide a data latch circuit including anti-fuse elements, which is capable of being manufactured with a reduced number of transistor elements and thus with reduced costs and reduced occupied area.
The present invention provides a data latch circuit including: a voltage selection block for selecting one of a normal operating voltage supplied from a first power source and a programming voltage supplied from a second power source, to output a selected voltage through a voltage selection node; a first first-conductivity-type MOSFET including a source and a backgate connected together to the voltage selection node, a gate connected to a first output terminal, and a drain connected to a second output terminal; a second first-conductivity-type MOSFET including a source and a backgate connected together to the voltage selection node, a gate connected to the second output termin
NEC Electronics Corporation
Nguyen Long
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