Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2011-04-19
2011-04-19
Shalwala, Bipin (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S204000, C327S333000
Reexamination Certificate
active
07928950
ABSTRACT:
The present invention provides a data latch circuit which can operate stably with a low-amplitude signal, which consumes less electric power, and which is resistant against the variation in TFTs.When an analog switch is turned on, a data signal is inputted to a gate electrode of an n-channel TFT and, at this time, VDD is supplied to an input terminal of an inverter. When the analog switch in turned off, the n-channel TFT is turned on or off depending on a level of the data signal. When the data signal is at an H level, the n-channel TFT is turned on and VSS is supplied to the input terminal of the inverter. When the data signal is at an L level, VDD is supplied to an input terminal of the inverter. Therefore, only VDD and VSS levels are applied to the input terminal of the inverter.
REFERENCES:
patent: 6774419 (2004-08-01), Kimura
patent: 7006068 (2006-02-01), Haga
patent: 7042447 (2006-05-01), Numao
patent: 7268756 (2007-09-01), Koyama et al.
patent: 7327169 (2008-02-01), Osame et al.
patent: 7352604 (2008-04-01), Shionoiri et al.
patent: 7528816 (2009-05-01), Tanaka et al.
patent: 2002/0015032 (2002-02-01), Koyama et al.
patent: 2002/0140663 (2002-10-01), Matsumoto
patent: 2003/0063079 (2003-04-01), Abe et al.
patent: 2003/0076149 (2003-04-01), Haga
patent: 2003/0210219 (2003-11-01), Osame
patent: 2004/0041764 (2004-03-01), Koyama et al.
patent: 2004/0095159 (2004-05-01), Kimura
patent: 2004/0100318 (2004-05-01), Lim
patent: 2004/0155698 (2004-08-01), Kimura
patent: 2004/0257117 (2004-12-01), Kimura
patent: 2004/0257136 (2004-12-01), Osame et al.
patent: 2005/0012731 (2005-01-01), Yamazaki et al.
patent: 2005/0099068 (2005-05-01), Kimura
patent: 2006/0238399 (2006-10-01), Mizukami et al.
patent: 2007/0109282 (2007-05-01), Kida et al.
patent: 2008/0150587 (2008-06-01), Osame et al.
patent: 1411150 (2003-04-01), None
patent: 1 643 482 (2006-04-01), None
patent: 2000-352957 (2000-12-01), None
patent: 2005/004102 (2005-01-01), None
Chinese Office Action received Mar. 20, 2009 in Chinese Application No. 200610077259.1 with Full Translation (19 pages).
European Patent Office Search Report (European Patent Application No. 06007517.3), 9 pages, mailed Jun. 12, 2009.
Osame Mitsuaki
Ueno Tatsuro
Fish & Richardson P.C.
Fry Matthew A
Semiconductor Energy Laboratory Co,. Ltd.
Shalwala Bipin
LandOfFree
Data latch circuit, driving method of the data latch... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data latch circuit, driving method of the data latch..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data latch circuit, driving method of the data latch... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2717613