Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2000-12-15
2003-12-09
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S203000
Reexamination Certificate
active
06661270
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a data latch circuit. More specifically, the present invention relates to a data latch circuit capable of latching data at high speed in response to a plurality of clock signals, and also relates to a method for driving such a high-speed data latch circuit.
2. Description of the Related Art
There is a Data latch circuit which latches data in response to the output from an OR-gate receiving a plurality of clock signals. For instance, the latch circuit is employed in such a case that a data latch circuit is operated at high speed under condition that only a clock signal having a low frequency may be supplied. Such condition is that, for instance, when a semiconductor device containing a data latch circuit is tested by way of a tester which can perform the test with a low frequency.
Into such a data latch circuit, two clock signals are supplied, the frequencies of which are equal to each other, but the phases of which are different from each other by “&pgr;”. A signal produced by OR-gating these two clock signals owns a frequency two times higher than the low frequency of the clock signal. Even when only the clock signal having the low frequency can be supplied, the semiconductor circuit can be operated at high speed in a similar manner to the case where a clock signal having a high frequency is used.
FIG. 11
shows such a semiconductor circuit. The semiconductor circuit of the related art includes a NOR gate
101
. Both a first clock signal line
102
and a second clock signal line
103
are connected to the input terminal of this NOR gate
101
.
A first clock signal “A” is supplied to a first clock signal line
102
. The first clock signal line
102
corresponds to such a signal line used to supply a clock signal to a plurality of circuits (circuits other than a flip-flop
104
are not shown). A second clock signal “B” is supplied to the second clock signal line
103
. The second clock signal line
103
corresponds to such a signal line connected to a plurality of circuits (circuits other than the flip-flop
104
are not shown). The NOR gate
101
produces a local clock signal “C” having a NOR logic between the first clock signal “A” and the second clock signal “B”, and then outputs this produced local clock signal “C” to another flip-flop
106
.
The flip-flop
104
contains both a master flip-flop
105
and the slave flip-flop
106
. The local clock signal “C” is inputted to both the master flip-flop
105
and the slave flip-flop
106
.
An input signal “D” is entered into the master flip-flop
105
. The master flip-flop
105
fixes a latch signal “E” after the voltage of the local clock signal “C” has been transferred from an “LO” voltage to a “HI” voltage, for a time duration during which the voltage of the local clock signal “C” is maintained at the “HI” voltage. Even when the input signal “D” is varied while the voltage of the local clock signal “C” is maintained at the HI voltage, the latch signal “E” is not varied. On the other hand, while the voltage of the local clock signal “C” is maintained at the “LO” voltage, the master flip-flop
105
directly outputs the data of the input signal “D” as the latch signal “E”.
The slave flip-flop
106
latches the data of the latch signal “E” when the local clock signal “C” rises. At this time, the slave flip-flop
106
receives the data held by the master flip-flop
105
. Even after the voltage of the local clock signal “C” has been returned to the “LO” voltage, the slave flip-flop
106
maintains to hold the data of the latch signal “E”. The slave flip-flop
106
continuously holds the latched data until the local clock signal “E” rises at the next time. The slave slip-flop
106
outputs the held data as an output signal “F”.
In particular, such a semiconductor circuit may be used as a semiconductor circuit selectively operable in the normal operation mode and the test mode. In the normal operation mode, the semiconductor circuit is operated in response to a clock signal employed in the semiconductor device. The test mode corresponds to such an operation mode under which the semiconductor circuit is tested. At this time, the clock signal is supplied by a tester.
There are some cases that the maximum operating frequency of the normal operation mode is higher than such a frequency which can be supplied by the tester. For example, the following case may be conceived. That is, the maximum operating frequency of the normal operation mode is equal to 200 MHz, whereas the maximum frequency of the clock signal which can be supplied by the tester is equal to 100 MHz.
In such a case, as to the semiconductor circuit shown in
FIG. 11
, the frequency of the clock signal supplied from the tester is multiplied and then the semiconductor circuit is operated based upon this clock signal having the multiplied frequency. Thus, even in such a case that the maximum operating frequency (for example, 100 MHz) of the tester is lower than the maximum operating frequency (for example, 100 MHz) of the semiconductor circuit, the functions of the semiconductor circuit can be tested by this tester.
The semiconductor circuit shown in
FIG. 11
may be operated under better condition by using the clock signal having the low frequency in the test mode. However, this semiconductor circuit is erroneously operated in such a case that the clock signal having the high frequency is supplied in the normal operation mode.
The reason why such an erroneous operation of the semiconductor circuit occurs is given as follows: That is to say, since the capacity of the signal line used to supply the clock signal is large, the transfer time of the clock signal is prolonged. Alternatively, the waveform of the rising signal portion of the clock signal is deformed.
In the known semiconductor circuit indicated in
FIG. 11
, the reason why the capacity of the signal line used to supply the clock signal is increased is that this known semiconductor circuit employs the NOR gate
101
. In this NOR gate
101
, the capacity of the input terminal is large. Therefore, both the capacity of the first clock signal line
102
and the capacity of the second clock signal line
103
are increased. Increasing of the capacity owned by the signal line may probably induce the occurrence of an erroneous operation in case that the semiconductor circuit is operated at high speed. Such a semiconductor circuit is desired which may latch data in response to a plurality of clock signals, while a capacity of a signal line is reduced.
Also, in the known semiconductor circuit indicated in
FIG. 11
, the output of the NOR gate
101
is connected to both the master flip-flop
105
and the slave flip-flop
106
. This NOR gate
101
requires such a drive-ability by which both the master flip-flop
105
and the slave flip-flop
106
may be driven in a proper condition. Such a fact that the maximum drive-ability of a logic gate under use is large may constitute a demerit with respect to a high-speed operation of a semiconductor circuit.
Accordingly, such a semiconductor circuit capable of latching data in response to a plurality of clock signals, while the maximum drive-ability of a logic gate under use is reduced, is wanted in this technical field.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor circuit for latching data in response to a plurality of clock signals, while a capacity of a signal line used to supply these clock signals is decreased. Another object of the present invention is to provide a semiconductor circuit for latching data in response to a plurality of clock signals, while the maximum drive-ability of a logic gate under use is decreased. The OR-gated result obtained from the first clock signal and the second clock signal is not inputted to the master flip-flop of the data latch circuit of the present invention. The load of the clock signal lines can be reduced.
signal (a) and the second clock signal (c).
REFERENCES:
patent: 4495628 (1985-01-01), Zasio
patent: 4
Choate Hall & Stewart
Lam Tuan T.
NEC Electronics Corporation
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