Measuring and testing – Speed – velocity – or acceleration
Patent
1996-01-22
1997-02-18
Williams, Hezron E.
Measuring and testing
Speed, velocity, or acceleration
73491, 7351401, 7351417, 364566, G01P 1500
Patent
active
056043082
ABSTRACT:
A digital circuit for adapting the output of a closed-loop accelerometer to a utilization circuit where the cycle time of the rebalance loop of the accelerometer is unrelated to the cycle time of the utilization circuit. A register receives and stores a digital value representative of measured acceleration and a bank of serially-arranged divide-by-two counters accepts the output of the rebalance loop clock. A gate arrangement makes one-by-one correlations between the states of the register and the outputs of the divide-by-two counters. A trigger circuit receives the gate outputs, providing a pulse when triggered by a downgoing edge of a square wave output of the gate array. A counter receives the pulse stream and is gated, in turn, in accordance with the cycle time of the utilization circuit so that the accelerometer data employed therein is representative of the portion of the acceleration occurring during a cycle of the utilization circuit.
REFERENCES:
patent: 3877313 (1975-04-01), Ferriss
patent: 4282470 (1981-08-01), Reynolds
patent: 5235330 (1993-08-01), Sewell
patent: 5243544 (1993-09-01), Schoess
patent: 5367542 (1994-11-01), Guo
Articles: Louis E. Frenzel, Jr., Digital Counter handbook, pp. 237 through 241 (1981); Don Lancaster, TTL Cookbook, pp. 87, 284 through 291; Texas Instruments, TTL Devices, pp. 3-393 through 3-399 (1983).
Mark John G.
McLane Daniel P.
Tazartes Daniel A.
Wyse Stanley F.
Kramsky Elliott N.
Litton Systems Inc.
Moller Richard A.
Williams Hezron E.
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