Data interface apparatus for multiple sequential processors

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G06F 300

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active

041492420

ABSTRACT:
Apparatus is disclosed for transferring data between multiple peripheral processors (PPs) which are operating under control of a host processor in a multi-processor computer system. In a high data rate application a number of dedicated special purpose PPs are arranged in fixed sequence to provide individual data processing steps. A data path is provided between each PP data memory and the next. A PP transfer unit associated with each PP data memory controls data transfer simultaneously between all PPs. Separate read/write address mapping is provided for each PP data memory. Control information may be associated with each mapped PP data memory location to provide logic functions and data rearrangements during the transfer process. Data from several PPs may be interleaved or may be logically or arithmetically combined with other PP data or constant information.

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