Data input circuit having latch circuit

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Details

364939, 364950, 3649504, G06F 300, G06F 1300

Patent

active

049998072

ABSTRACT:
A data input circuit provided in a data processing equipment is disclosed. The input circuit includes a timing circuit generating a latch pulse in asynchronism with a read request signal generated by a CPU and a latch circuit latching input data in response to the latch pulse. The data latched in the latch circuit is transferred to a data bus in response to the read request signal. The input circuit further includes circuitry responsive to an access by the CPU for delaying the generation of the latch pulse such that the latch pulse is generated after the CPU stops to generate the read request signal. The latch circuit is thereby prevented from latching the input data while the read request signal is generated.

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patent: 4649512 (1987-03-01), Nukiyama
patent: 4654584 (1987-03-01), Gyles
patent: 4718036 (1988-01-01), Halbert et al.

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