Data input circuit and method for synchronous semiconductor...

Details Data input circuit and method for synchronous semiconductor... Data input circuit and method for synchronous semiconductor...

2002-02-21

2004-04-27

Mai, Son (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C365S219000

Reexamination Certificate

active

06728162

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
Disclosed is a synchronous semiconductor memory device. In particular, a circuit and a method for writing data into a synchronous semiconductor memory.
2. Discussion of the Related Art
The operational speed and performance of a synchronous dynamic random access memory SDRAM is improved over a dynamic random access memory (DRAM) when the SDRAM is operated in synchronization with an external system clock and there are frequent sequential data read/write operations.
The operational speed and performance of an SDRAM is further improved when both the rising and falling edges of the system clock is used in reading and writing data, i.e., the clock rate is effectively doubled. This memory device is called the double data rate (DDR) SDRAM. In a DDR SDRAM, a strobe signal, commonly referred to as “DQS”, is used in conjunction with the system clock to strobe and clock memory data.
U.S. Pat. No. 6,078,546 to Lee discloses a synchronous semiconductor device having a double data rate input circuit which allows data to be written in the device in response to a clock signal and a data strobe signal.
FIG. 1A
shows an input circuit disclosed in the '546 patent which stores a pair of data which is synchronized with either the system clock signal or the data strobe signal. Referring to
FIG. 1A
, an externally applied data strobe signal DS is received during a data write operation. An edge detector
300
detects an edge of the data strobe signal DS and generates first and second internal strobe signals DS
1
and DS
2
in synchronization with rising and falling edges of the data strobe signal DS, respectively. The signals DS
1
and DS
2
are used to strobe the odd and even data into data registers
303
A and
303
B, respectively. A second edge detector
301
detects an active edge of a system clock. A delay circuit
304
delays the output of the second edge detector
301
and the delayed clock signal CLKD is used to output the data from the data registers to write driver
305
.
FIG. 1B
shows the structure of the data register
303
. Referring to
FIG. 1B
, the first or the odd data of the pair of data is input first to unit cell R
1
, where it is strobed by strobe signal DS
1
and the complement of DS
1
. The output of R
1
is fed to R
2
. Unit cell R
3
receives the even or the second data bit of the data pair. Unit cells R
2
and R
3
are both first strobed by a strobe signal DS
2
(AWR) and its complement. DS
2
(AWR) is a product of the DS
2
strobe signal and the write pulse to synchronize the strobe signals to the write operation. The odd and even data pair is then output with clocking by the delayed clock signal CLKD.
FIG. 2
shows a timing diagram of the data write operations of the circuit of FIG.
1
A. The timing diagram shows the strobe and clock operations for a 4-bit data string input from DIND. The storage cell R
1
stores the odd numbered data D
0
and D
2
of the data string in synchronism with internal data strobe signals DS
1
and its complement/DS
1
. The storage cell R
3
stores the even numbered D
1
and D
3
in synchronism with strobe signals DS
2
and its complement/DS
2
. The write drivers are activated with the first active external clock signal CLK after the write command WR. Case I illustrates that the data reaches the register circuit
303
with the valid data strobe signals inputted after reference clock signal CLK(
0
), namely in a case where the value of the t DQSS is maximum. Case II illustrates that data reaches the register circuit
303
with the valid data strobe signals inputted before the reference clock signal CLK(
0
), namely, in the case where the value of the t DQSS is minimum. The disclosure of U.S. Pat. No. 6,078,546 in its entirety is incorporated by reference herein.
As operational speed of memory devices are further increased, the timing margin between the external system clock and the data strobe signal DS becomes shorter. Accordingly, a need exists for an improved system and method for writing a string of data into a synchronous memory device with increased timing margin.
SUMMARY OF THE INVENTION
According to the present invention, a circuit for receiving data for a synchronous semiconductor memory device is provided, comprising: a strobe generator having a flip flop and a plurality of logic gates for generating S(n) internal strobes based on an external strobe signal, each of the S(n) internal strobes having a latch-triggering transition occurring one after another in response to the external strobe signal; a plurality of latches for receiving an n-bit data, including at least one set of latches being clocked by the S(n)th internal strobe and another set of latches for receiving the outputs from the one set of latches, the another set of latches being clocked by an internal clock signal having a period longer than that of an external clock signal and a data write driver for receiving the outputs of the another set of latches and for driving the n-bit data into memory cells of the memory device under clocking control of the external clock.
The circuit further including a frequency divider for dividing by two the external clock signal to derive the internal clock signal for clocking the another set of latches. The plurality of latches includes a first set of L(n−1) latches for receiving respective (n−1) bits of an n-bit data, each of the first set of latches being clocked by a respective S(n−1) internal strobe, and a second set of latches configured to receive respective outputs of the first set L(n−1) latches and the nth bit data, the second set of latches being clocked by the S(n)th internal strobe, and a third set of latches for receiving respective outputs of the second set of latches, the third set of latches being clocked by the internal clock signal, the external clock signal being derived from an external memory controller.
Further, the flip flop in the strobe generator is configured as a frequency divider for dividing by two the external strobe signal, and the complementary outputs of the flip flop are applied to the inputs of four AND gates to produce the S(n) internal strobes. Preferably, the semiconductor memory device is a double data rate SDRAM, and wherein (n) is equal to four (4).
A circuit is also provided for receiving data to be written in a synchronous semiconductor memory device, comprising: a first set of latches for receiving an n-bit data upon transition of an internal strobe signal; a counter for counting the number of transitions of the internal strobe signal and for outputting an indicating signal upon counting the end of a string of internal strobe signals; a second set of latches for receiving the outputs of the first set of latches, the second set of latches being clocked by the indicating signal; and a third set of latches for receiving the outputs of the second set of latches, the third set of latches being clocked by a clock signal derived from a system clock, wherein the counter is clocked by a first clock derived from the system clock.
Preferably, the first clock is derived from a falling edge of the system clock, and a counter reset signal is generated based on the falling edge of the system clock after a write command, the counter reset signal for resetting the counter. The first set of latches receives the n-bit data serially under clocking control by the internal strobe signal. The second set of latches receives the latched n-bit data in parallel, wherein the indicating signal is output by the counter upon detecting two transitions of the internal strobe signal, and (n) is equal to four.
Accordingly to another aspect of the invention, a circuit for receiving data to be written in a synchronous semiconductor memory device is provided, comprising: a first set of latches for receiving an n-bit data upon transition of an internal strobe signal; a counter for counting the number of falling edges of an external strobe signal and for outputting a counting signal; an indicating signal generator for receiving the counting signal outputted fro

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