Data I/O circuit with higher integration density for DRAM

Details Data I/O circuit with higher integration density for DRAM Data I/O circuit with higher integration density for DRAM

1985-03-01

1987-02-24

Hecker, Stuart N.

Static information storage and retrieval

Addressing

Sync/clocking

365190, 365239, G11C 700, G11C 1124

Patent

active

046462724

ABSTRACT:
A data input/output circuit operates in an operation cycle in which, when a first latch circuit connected to a first data bus issues 1-bit information to a data output buffer, next 1-bit information is latched in a second latch circuit connected to a second data bus and simultaneously the first data bus is precharged, and in an operation cycle in which, when 1-bit data stored in the second latch circuit is issued to the data output buffer, next 1-bit data is latched in the first latch circuit and simultaneously the second data bus is precharged. Therefore, when one of the latch circuits issues data to the data output buffer, the other latch circuit latches data and is in a standby condition. An access time in which to issue data from bit lines to the data buses is greatly reduced notwithstanding the only two data buses are employed. Accordingly, the chip area occupied by the data buses can be reduced appreciably.

REFERENCES:
patent: 4562555 (1985-12-01), Ouchi et al.
patent: 4567579 (1986-01-01), Patel et al.

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