Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-03-16
2001-05-29
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185010, C365S145000
Reexamination Certificate
active
06240013
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a data holding apparatus that is capable of a high speed response and that does not require a use of a power source to hold data.
2. Description of the Related Art
SRAM (Static Random Access Memory) using MOSFET type transistors is known as a data holding apparatus.
FIG. 30
is a circuit diagram of an example of a memory cell comprising a conventional SRAM. A memory cell MC is equipped with a pair of memory transistors MT
1
and MT
2
and a pair of resistors R
1
and R
2
. Additionally, the memory cell MC is connected to a pair of select transistors ST
1
and ST
2
(in combination defined as a “a select transistor pair STP”) by a pair of bit lines BL and BLB
1
(in combination defined as a “bit line pair BLP”). The select transistor pair STP is connected to word lines WL. A number of such memory cells are placed in an array in a SRAM.
To write data in the memory cell MC of a SRAM, a pair of electric potentials that corresponds to data to be written is applied to the bit line pair BLP. To write Data “0”, for example, a low electric potential “L” is applied to the bit line BL while a high electric potential “H” is applied to the bit line BLB. Next, the “H” electric potential is applied to word lines WL to turn ON the select transistor pair STP. This results in the memory transistor MT
1
to go ON and the memory transistor MT
2
to go OFF. Now, Data “0” is written in the memory cell MC. To write Data “1” in the memory cell MC, the high electric potential “H” is applied to the bit line BL and the low electric potential “L” is applied to the bit line BLB.
Subsequently changing the electric potential of the word lines WL to “L” turns the select transistor pair STP OFF and the memory cell goes into a standby state. In the standby state, written data is retained in the memory cell MC because of its self-latching capability. To read data, the electric potential “H” is applied to the word lines WL to turn ON the select transistor pair STP and to detect the voltage that appears in the bit line pair BLP. The content of the data is thus read out.
However, the above described SRAM had several problems. Because a voltage had to be consistently applied to the circuit to hold data, a power source was constantly required even when no data was being written or read. Consequently, SRAM consumed and wasted an electric power. Moreover, there was an inconvenience that a stored data was lost whenever the power source failed for any reason including an accident.
One of the solutions to the above noted problems may be to use a non-volatile storage element EEPROM as a memory element. However, this is infeasible for a data holding apparatus that must respond at a high speed since EEPROM requires a long time to write data.
SUMMARY OF THE INVENTION
Accordingly, it is an objective of the present invention to provide a memory device that substantially obviates one or more of the problems due to limitations and disadvantages of the conventional data holding apparatus such as SRAM. It is another object of the present invention to provide a data holding apparatus that is capable of a high speed response and that does not require a use of a power source to hold data.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention provides a data holding apparatus comprising memory cells. Each memory cell includes first and second transistors, where at least the first transistor is a ferroelectric transistor having a floating gate and a ferroelectric layer between the gate insulating layer and the control gate. Each of the first and second transistors applies a positive feedback to the other of the first and second transistors to maintain an ON or OFF state of the other transistor, and the memory cell holds data defined by the ON or OFF states of the first and second transistors.
By applying a voltage that corresponds to data to be written directly to the floating gate, the ferroelectric transistor is enabled to be in the ON or OFF state that corresponds to the data at the same speed and stability as a conventional transistor that without the floating gate and a ferroelectric layer. Therefore, data can be written into the memory elements at a very high speed and a very high stability. The voltage applied to the floating gate and the voltage of the control gate trigger the ferroelectric layer to be in a polarized state that corresponds to the ON or OFF state of the subject ferroelectric transistor. Moreover, because the voltage is applied directly to both terminals of the ferroelectric layer, the ferroelectric layer can inverse its polarized state reliably and the power source voltage can be lowered effectively. Furthermore, the polarized state of the ferroelectric layer is maintained even when the power source of circuits is cut off. When the power source is turned back on, the ferroelectric transistor returns to the ON or OFF state that corresponds to the polarized state maintained by its ferroelectric layer. Consequently, the power source is not needed to hold data.
The memory element according to one embodiment includes first and second transistors where at least one of them is a ferroelectric transistor. The control gate of the first transistor is connected to the drain the second transistor and the control gate of the second transistor is connected to the drain of the first transistor, so that the first and second transistors provide positive feedback to each other so the ON or OFF state of the transistors are different from each other. Moreover, the electric potential of a control gate of a ferroelectric transistor in a stationary state after data are written is almost the same as that of a floating gate when data are being written. As a result, electric potentials of both terminals of the ferroelectric transistor do not change even when the floating gate returns to a floating state at the completion of the write process.
The data holding apparatus according to a second embodiment is equipped with first and second power source supply lines and data lines for inputting and outputting data. The drain of the first and second transistors are connected to the first power source supply line by first and second pull-up resistors, respectively. The source of the first and second transistors are connected to the second power source supply line. When writing data, the data lines are connected to floating gates and disconnected from the drains. When reading data, data lines are connected to the drains, and disconnected from the floating gates. Consequently, a non-volatile memory unit that is capable of securely holding data can be constructed from a relatively few number of elements.
The data holding apparatus according to a third embodiment is similar to the second embodiment and both the first and second transistors are ferroelectric transistors. The data holding apparatus is equipped with data lines that obtain mutually different logical values defined as the first and second data lines. When writing data, the first and second data lines are connected to corresponding floating gates of the first and second transistors, and disconnected from the corresponding drains of the first and second transistors. When reading data, the first and second data lines are connected to the corresponding drains of the first and second transistors, and disconnected from the corresponding floating gates of the first and second transistors.
The data holding apparatus according to a fourth embodiment includes a first CMOS inverter equipped with the first and a third transistor, and a second inverter equipped with the second transistors and a fourth transistor. At least one of the first through fourth transistors is a ferroelectric transistor. The output terminal of the first CMOS inverter is connected to the input terminal of the second CMOS inverter, and the output terminal of the second CMOS inverter is connected to the input terminal of the first CMOS inverter to
Fears Terrell W.
Hogan & Hartson LLP
Rohm & Co., Ltd.
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