Data-hold timing adjustment circuit

Details Data-hold timing adjustment circuit Data-hold timing adjustment circuit

1994-03-16

1995-12-19

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327262, 327270, H03H 1126

Patent

active

054771781

ABSTRACT:
A data-hold timing adjustment circuit having resistance wires to which a power-supply voltage is supplied, formed along numerous flip-flops. MOS variable capacitors 3i and 4i (i=1 to n) are connected at one electrode to the data input end of the flip-flops and at another electrode to the resistance wires. The composite capacitance of the MOS capacitors becomes larger as the value of i increases, independent of the voltage level of the data input end of the flip-flops. When the potential of the data input end of the flip-flop shifts from a high/low level to a low/high level, this shift is delayed more as the value of i becomes larger, while the clock input to the flip-flop is delayed more as the value of i becomes larger.

REFERENCES:
patent: 4330750 (1982-05-01), Mayor
patent: 4644182 (1987-02-01), Kawashima et al.
patent: 4894791 (1990-01-01), Jiang et al.
patent: 5063313 (1991-11-01), Kikuda et al.
patent: 5097159 (1992-03-01), Seki et al.
patent: 5107153 (1992-04-01), Osaki et al.
patent: 5130564 (1992-07-01), Sin
patent: 5137202 (1994-05-01), Waizman

Affiliated with

Also associated with

Rating

Data-hold timing adjustment circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data-hold timing adjustment circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data-hold timing adjustment circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-994297