Data-handling system with operatively interconnected processors

Details Data-handling system with operatively interconnected processors Data-handling system with operatively interconnected processors

1980-02-14

1982-06-08

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

364200, H04J 308

Patent

active

043343058

ABSTRACT:
A number of data processors have access, via respective interfaces, to a common ring memory made up of cascaded shift-register sections. Each interface comprises a pair of shift registers or a pair of read/write memories one of which, at a given instant, is operatively connected to the ring memory while the other coacts with the processor, their roles being interchanged from time to time by a switchover signal from a logic network in response to an instruction from the associated processor. The logic networks of all interfaces receive clock pulses from a common time base and, optionally, may be able to inhibit temporarily the emission of such pulses pending completion of an exchange of information with the ring memory.

REFERENCES:
patent: 3755789 (1973-08-01), Collins
patent: 3787627 (1974-01-01), Abramson et al.
patent: 3790717 (1974-02-01), Abramson et al.
patent: 4002842 (1977-01-01), Meyr et al.
patent: 4042783 (1977-08-01), Gindi
patent: 4071824 (1978-01-01), Warren
IEEE Proceedings of the Annual Symposium of Computer Architecture, vol. 3, pp. 124-129, Jan. 19-21, 1976.

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