Data formatter for shifting data to correct data lanes

Details Data formatter for shifting data to correct data lanes Data formatter for shifting data to correct data lanes

2001-11-30

2004-03-23

Sparks, Donald (Department: 2187)

Data processing: vehicles, navigation, and relative location

Navigation

Determination of travel data based on the start point and...

C365S078000, C365S189120, C365S240000, C711S217000, C711S219000

Reexamination Certificate

active

06711494

ABSTRACT:

BACKGROUND
In computer systems, a central processing unit (CPU) may access memory by providing an address that indicates a unique location of a group of memory cells that collectively store a data element. A number of operations may be taken when performing an initial access to memory. These operations may make the initial access relatively slow. For example, certain control signals may be issued to begin the process. Next, the address may be sent to the memory. Then, the data itself may be transferred. Because of this operational overhead, or latency, the initial access to memory may take a relatively long time, e.g., four to seven clock cycles in many devices.
To reduce the latency of the memory, some memory devices read a block of data including four 64-bit words (256 bits or 32 bytes) from memory consecutively for each access. An advantage of this “burst access mode,” or “bursting,” is avoiding repetition of the overhead of the initial access for the subsequent three accesses. The subsequent accesses may be shortened to one to three clock cycles instead of four to seven clock cycles.
A memory device that supports bursting may not be byte-addressable. Instead of accessing a memory location at a specific byte address, the memory device may retrieve a multi-byte block of data elements. Some of the data elements in the block of data may not be valid for the request.
A data formatter may be used to take a multi-block of data from a source, such as a random access memory (RAM), and break up the multi-byte block into multiple smaller blocks. Each of the smaller blocks can then be sent to the appropriate local memory addresses.
A controlling program determines the size of each of the smaller blocks and their destination addresses. The smaller blocks may be broken up on any byte boundary within the larger block. The destination addresses may also be located at any byte boundary. This complicates the data formatter's responsibilities. No matter which byte lanes the data elements are in when they come from the providing RAM, the data formatter must ensure that these bytes are in the correct byte lanes for writing to a new address.
SUMMARY
A data formatter includes a shift register and a pointer manager. A providing random access memory (RAM) stores data from a multi-byte block of data, retrieved in a burst access operation to a memory, to be written to local memory addresses. The shift register receives data from the providing RAM and shifts that data in response to reading data from the providing RAM and writing data to a receiving first-in first-out (FIFO) memory. A pointer manager maintains a pointer that points to a first valid byte in a sub-block of data into the correct bytes lanes of the FIFO by moving the pointer as data is shifted into and out of the shift register.
The pointer manager generates indicators based on the pointer value which notify the controlling program that the shift register is full (or almost full) or empty (or almost empty).


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Microsoft Press Computer Dictionary, Third Edition, 1997, p. 433.

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