Data flow scheme for low power DRAM

Details Data flow scheme for low power DRAM Data flow scheme for low power DRAM

2011-07-12

2011-07-12

Nguyen, Dang T (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189150, C365S189160

Reexamination Certificate

active

07978525

ABSTRACT:
Circuits and methods to minimize power required for sensing and precharge of DRAMs have been achieved. A control circuit ensures that during READ operations the duration of sensing of DRAM cell and precharging is kept to a minimum. A test DRAM cell is used to determine the exact time required for data sensing. Furthermore no precharging is performed during WRITE-operations. In case data is changing from “1” to “0” or vice versa data lines are inverted accordingly during WRITE operation.

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