Data flow processor with data processing and next address determ

Details Data flow processor with data processing and next address determ Data flow processor with data processing and next address determ

1993-02-01

1994-11-08

Kulik, Paul V.

Boots, shoes, and leggings

364DIG1, 36423222, 395775, 395800, G06F 1582

Patent

active

053634918

ABSTRACT:
A data flow processor which is so constructed that the destination node number in a program memory is stored at a relative address from, for example, a stored address of the present instruction, and a storing address for the next instruction is obtained by adding the relative address of the next instruction to the address of the present instruction. Hence, an amount of data of storing address of instruction to be executed next and included in the respective instructions is reduced, whereby an amount of hardware at the program memory is reduced and the memory access time is contracted.

REFERENCES:
patent: 4145733 (1979-03-01), Misunas et al.
patent: 5093919 (1992-03-01), Yoshida et al.
patent: 5218706 (1993-06-01), Komori et al.
Encyclopedia of Computer Science and Engineering, 2nd ED Ralston et al, 1983 p. 17.
"An Architecture of a Data Flow Machine and its Evaluation," pp. 486-490, Shimada et al IEEE Comcon 1984 Spring.

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