Data flow processor with a full-to-half word convertor

Details Data flow processor with a full-to-half word convertor Data flow processor with a full-to-half word convertor

1991-04-22

1994-08-23

Bowler, Alyssa H.

Boots, shoes, and leggings

36493111, 36494063, 3649513, 364DIG2, G06F 1300, G06F 1338, G06F 1500, G06F 1582

Patent

active

053415060

ABSTRACT:
In a dataflow processor, double precision data segments of higher and lower significant bits and like segments of single precision data are read out of a memory and appended with a tag to form packets. The packets are forwarded to a ring bus to which computing modules are connected. Each module includes an interface which forwards the packet onto the bus if another module is the destination. If the packet is destined to the own module, the packet is split into a tag and a data segment. If the tag indicates that the data segment is double precision data, it is assembled with the companion segment of a previous packet into a double precision data word. Otherwise, it is translated to a single precision data word of the same bit width as the double precision data word. A data set is formed by successive double precision data words or by successive single precision data words. A variable is generated indicating if the data words in each set are double or single precision data and indicating what computation is to be performed thereon. Computed double precision data are separated into data segments of higher and lower significant bits and a tag is appended to each of the separated data segments to form a packet and computed single precision data are translated to data segments of single precision data segment and a tag is appended to it to form a data packet. Each computed data packet is forwarded back to the bus for further computations.

REFERENCES:
patent: Re34052 (1992-09-01), Hester et al.
patent: 4663732 (1987-05-01), Robinson
Watson, et al. "A practical data flow computer", Computer, vol. 15, No. 2, Long Beach, U.S., Feb. 1982, pp. 51-57.
Thurber, et al. "Systematic Approach to Design of Digital Bussing Structures", Fall Joint Computer Conference, 1972, p. 731.

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