Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
1998-06-18
2002-04-09
Eng, David Y. (Department: 2155)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
Reexamination Certificate
active
06370634
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to computer technology, particularly it concerns computer systems.
The invention has application in both engineering and technical calculations for space and aviation technologies, geodesy, hydrometeorology and other fields which require high performance computations.
2. Description of the Related Art
There is a known computer system which contains central input-output processors, a switch, a main memory unit, a control panel, peripheral memory devices with control blocks and data transmission processors (SU, A, 692400).
In this system Von Neumann's principle of data processing is used. Every central processor contains a conforming (conjugating) unit, a block for performing procedures, an indexing block, a block for value retrieving, a block for processing strings, an arithmetic-logical unit, a block of the basic registers, a unit for instructions forming, a control unit, a unit for the distribution of stack addresses, a buffering stack of operands, an associative memory unit, a unit for transformation of the mathematical addresses into the physical ones, a block of memory for buffering instructions, a block for analysis of interrupts.
The arithmetic-logical unit includes: blocks for multiplication, addition, division, code transformation and logical operation performing. These blocks work in parallel and independently from one another, providing parallel data processing within each processor and using the natural parallelism of the programs under execution.
However, implementation of this unit has shown that, in practice, the use of Von Neumann's principle of computation organization requires high unproductive expenditures of hardware and computing capacity to provide parallel work of several executive devices. These expenditures, first of all, are related to the fact that to form independent sequences of instructions from the program in execution it is necessary to do a preliminary survey of program segments (of the average length up to 30 instructions) and a dynamic planning of executing units loading with the help of special hardware means, which was described in detail (Babayan B.A. “Main results and perspective of development of the “Elbrus” architecture”, Applied Computer Science works collection, vol. 15, Moscow, Finance and Statistics, 1989, pp. 100-131).
Due to this fact the hardware becomes considerably more complicated, having simultaneously a low real increase of performance. Parallelism of program processing on several executive devices is restricted and does not spread on the whole program (the segments of parallel processing do not exceed 10-20 instructions). Moreover, the process of extraction of instructions from the program for parallel execution itself requires a large amount of additional hardware and working time of the processor. This is another factor of the decrease in performance.
There is a known device which contains units of common memory, units of central input-output processors, using Von Neumann's principle of computation processing and parallel work of several executive devices, being parts of central processors. This device achieves program processing parallelism by means of forming an extensive instruction which includes operations for the simultaneous start of several arithmetic units (SU, A, 1777148).
Formation of such an instruction is conducted by static operation planning during the program translation stage. Here, the number of operations of the instruction being executed in parallel is limited (it does not exceed 7).
However, this device does not achieve high performance based on the internal parallelism of the programs in execution because of limited parallelism of operations in execution in the device and a cessation of execution when all the operands necessary for a computation are not available. This problem arises from the restrictions set by the translator and also in the case when the variable position in memory depends on computation conditions. Also, this device has a complicated translator structure and a large amount of the hardware to conduct local parallelism of computation.
There is a known computer system which contains a switch and N processor units. In such a system the first control outputs and address outputs of the i-th processor unit (i=1, . . . ,N) are connected correspondingly with the i-th input of the first control input group and with the i-th input of the group of the address switch inputs. The first and second informational outputs of the i-th processor unit are connected with the corresponding i-th input of the group of informational switch inputs. The first informational, address, control and the second informational, address, control inputs of the i-th processor unit are connected with the first and second informational system inputs. The first control input of this system is connected with the control switch input and with the third control input of the i-th processor unit. The switch control output is connected with the fourth control input of the i-th processor unit. The third informational output of this unit is connected with the first informational output of the system. The computer system can have a second informational output and a third informational input (U.S. Pat. No. 4,814,978).
For computation organization this system uses the data flow principle, which provides effective loading for each processor unit and high total performance. This is achieved by means of parallel instruction execution in all sections of the program and is supported by a programmable computation organization. The program is mapped as a graph, each node of which is an instruction and arcs show the direction of data transmission. Each of the processor units, mutually connected through the switch, executes a local section of the program. The processor units work in parallel and the necessary synchronization between sections of the program is carried out by means of the data transmit through the switch. Parallelism is achieved by the partition of the program during translation into separate linked sections, which leads to a waste of time and adecrease in device performance. Thus, device performance depends greatly on the programming system capability to segregate sections (sub-programs), which are weakly linked to one another. in the original program and is quite time-consuming on the user (programmer) side.
These disadvantages do not allow the full internal parallelism of the programs in execution to be realized in this device and as a result do not achieve high performance based on this parallelism and the data flow principle.
SUMMARY OF THE INVENTION
The invention is based on the problem of creating a computer system which would achieve increased performance by means of simultaneous access of each processor unit to the entire program in execution and through automation of the process of computational means distribution.
The problem is solved this way. The computer system contains a switch, N processor units, a second informational output and a third informational input. The first control output and address output of the i-th processor unit (i=1 . . . N) are connected correspondingly with the i-th input of the first group of switch control inputs and with the i-th input of the group of switch address inputs. The first and second informational outputs of the i-th processor unit are connected with the corresponding input of the group of switch informational inputs. The first informational, address, and control inputs and the second informational, address, and control inputs of the i-th processor unit are connected with the first and second informational inputs of the system. The first control input of the system is connected with the control input of the switch and with third control input of the i-th processor unit. The control output of the switch
2
is connected with the fourth control input of the i-th processor unit. The third informational output of the i-th processor unit is connected with the first informational
Berezko Alexandr Mikhailovich
Burtsev Vsevolod Sergeevich
Erschov Vladimir K.
Flodorov Vjacheslav B.
Khailov Igor K.
Costa John G.
Eng David Y.
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